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x58 -> legacy pci express endpoint

Discussion in 'Videocards - NVIDIA GeForce Drivers Section' started by boombastik, Jun 13, 2016.

  1. boombastik

    boombastik Master Guru

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    I have read intel's pdf about x58 chipset. U can find it online.
     
  2. pittiez

    pittiez Member

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    there is a thread about irq/msi showthread.php?t=378044 but like HPET some people are for it and some are against it

    as for MSI not being default? cause IRQ is the safe bet and its better to not take risks on a setting that might affect some people negatively

    holly carp i cant post links yet
     
  3. pittiez

    pittiez Member

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    i had MSI mode enabled before, but had to reenable after updating my nv drivers to Hotfix Driver 368.51

    [​IMG]

    all pcie bus except #3 say pcie express end point and #3 (2nd 16x slot) says legacy pci express endpoint
     
  4. Astyanax

    Astyanax Ancient Guru

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    There is no "current" reason for it, have Queried nvidia on the subject and they can't even remember why they do, but some digging I discovered that Nforce chipsets were 'incompatible'.
     

  5. artina90

    artina90 Active Member

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    Same behavior on X299, the port type is listed as legacy.
    Performance is great though, both in terms of framerate and frametimes and in line with the other 1080s out there:

    [​IMG]
     
  6. mbk1969

    mbk1969 Ancient Guru

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    To all gurus triggered by the word "legacy":

    https://www.mindshare.com/files/resources/MindShare_Intro_to_PCIe.pdf

    - it is just a term for endpoints with Input/Output capabilities.
     
  7. Astyanax

    Astyanax Ancient Guru

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    I found that too,

    The most important part

    Interrupt-capable legacy devices may support legacy style interrupt generation using message requests but must also support MSI generation using memory write transactions.

    I don't get where bombastik read in the x58 notes that interrupts fire on the ich10r, the x58 itself has interrupt registers, and if it were returning northbridge interrupts via the dmi connected ich10 it would be far to high in latency.

    Section 8.1 completely rebukes his claims that interrupts are routed to the ICH, and infact its the reverse, ICH interrupts from PCX devices are fired on the IOH as described in section 8.4


    Edit

    Bombastik is correct, but in only a single scenario, when the system is configured to PIC, apic is disabled and the interrupts are fowarded to the ICH10,

    This is NOT possible while maintaining multicore cpu capability, and also limits your system to 17 interrupts (0-16)

    In all other cases, the IRQ is converted to an MSI via the IO/APIC and sent to the CPU.
     
    Last edited: Oct 12, 2018

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