It lowers the actual working frequency of CPU. It seems to me that simple sleep and C-states do a better job of power saving than lowering the CPU frequency.
What I read from anandtech's article about skylake says that there is a voltage vs frequency graph, if you lower frequency by some point then you can't reduce voltage efficiently. That's why intel made duty cycling. Do you mean that the frequency is the same as or higher than before when cores are working in duty cycles, but since the clock will stop for cores for some fractions of time, the frequency is on average lower? And does this feature behaves differently on intel cpu and amd cpu? amd says ryzen can go between C0 and cc6 state in 100us, skylake does duty cycling once in 800us.
@mbk1969 I get what duty cycling is doing. The clock will stop sending signals to cores in some ratio of time, and therefore core frequency will approach 0Hz. And based on the power consumption formula p=c*v^2*f, instantaneous power consumption approaches 0w when instantaneous frequency approaches 0Hz with the same voltage. I think MS disable it by default because it makes frequency an unreliable value when measuring performance, because performance is lower even when people see the same frequency, and no one knows exactly how processors decide their duty cycles.
C states work in combination with SpeedStep to raise and lower clock rates, even Alderlake only runs the clocks as high as needed for the task at hand.
Finally found two articles by AMD that talks about duty cycling. The doi are 10.1109/ISSCC.2017.7870256 and 10.1109/ISSCC19947.2020.9063113 In the latter one about zen2, they say: "Additional support for run-time duty-cycle settings for 1/nth granularity divider options generated more frequency ranges for various market segments." I suppose ryzen mobile have smaller granularity because mobile devices are more sensitive to power management, while higher end chips never care for that.
@mbk1969 I am playing with bcdedit, are the time check intervals for p-state/c-state/autonomous activity window affected by useplatformtick/useplatformclock/disabledynamictick?
By useplatformclock - in case QueryPerformanceCounter/QueryPerformanceFrequency functions are used for time span measure.
There is a subgroup called Idle resiliency settings (2E601130-5351-4d9d-8E04-252966BAD054), do they also control when should cores go to c-state? Execution Required power request timeout (3166BC41-7E98-4e03-B34E-EC0F5F2B218E) by default is 4294967295s on ac and 300s on dc. Does it mean the power settings could be ignored for 6min on dc and 136 years on ac by default? I put 0s so that there is no timeout. IO coalescing timeout (C36F0EB4-2988-4a70-8EEE-0884FC2C2433) by deafult is 0ms on ac and 60000ms on dc. I put a large value, haven't feel any lags yet. Processor Idle Resiliency Timer Resolution (C42B79AA-AA3A-484b-A98F-2CF32AA90A28) is 0ms on every power plan by default. See no difference when changing the value, but I still put 1ms so that it is enabled.
I am sure it all relates to modern standby - https://docs.microsoft.com/en-us/wi...periences/prepare-software-for-modern-standby https://superuser.com/questions/118...-difference-between-display-system-awaymode-p Software can issue so called power requests to prevent display from turning off, to prevent system from going to sleep, to prevent the process to be closed by process lifetime management mechanisms. Request timeout sounds like a span for which the system waits for power requests to expire before change to another standby state. More or less relevant answer I found: Interrupt coalescing is a technique which “stores up” interrupts until an amount of work is pending then competes the tasks. This technique can improve system performance by an order of magnitude in certain workloads. The timeout is a measure of how long this technique is allowed to “store up” work until it is forced to complete the held tasks. Setting it to 0 removes this feature. This feature has been around for many years in network cards and UARTs (universal asynchronous receiver transmitters).
Some network adapters has an option called "transmission power" under device manager->the adapter->advance. Some don't have so many options due to driver. WIndows also has 4 power modes for network adapters in the power settings. The 4 modes are in hexadecimal when I go the the corresponding registry. Is the registry the hidden power setting in device manager, or are they individual settings?
https://docs.microsoft.com/en-us/previous-versions/windows/hardware/design/dn613985(v=vs.85) This doc directly states that MS just don't want users to touch the power settings, OEM are responsible for doing it.
@mbk1969 What does Allow Throttle States (3b04d4fd-1cc7-4f23-ab1c-d1337819c4bb) actually do? HP's doc says p-states "define a set of fixed operating frequencies and voltages" and throttle states "define a set of fixed frequency percentages that can be used to regulate the power consumption and the thermal properties of the processor" So throttle states are just regulating frequency but not voltage? I don't see the meaning of it because p-states already cover frequency and voltage.
There is an article that says throttle states is duty cycling for old processors without p-states: https://man.netbsd.org/acpicpu.4 If so, what about the processor duty cycling since skylake? How do they differ?
From the same article: While new duty cycling actually modulates the clock signal, as I take it. Upd: Here is PPM report of pwrtest tool (was available at MS site long ago) about my (weak/typewriter) rig: Code: InstanceName: ACPI\GenuineIntel_-_Intel64_Family_6_Model_76_-_______Intel(R)_Celeron(R)_CPU__J3160__@_1.60GHz\_2_0 Processor Performance States PerfStates: Max Transition Latency: 10 us Number of States: 24 State Speed (Mhz) Type ----- ----------- ---- 0 1601 (100%) Performance 1 1600 ( 99%) Performance 2 1520 ( 94%) Performance 3 1440 ( 89%) Performance 4 1360 ( 84%) Performance 5 1280 ( 79%) Performance 6 1200 ( 74%) Performance 7 1120 ( 69%) Performance 8 1040 ( 64%) Performance 9 960 ( 59%) Performance 10 880 ( 54%) Performance 11 800 ( 49%) Performance 12 720 ( 44%) Performance 13 640 ( 39%) Performance 14 560 ( 34%) Performance 15 480 ( 29%) Performance 16 480 ( 29%) Throttle 17 422 ( 26%) Throttle 18 360 ( 22%) Throttle 19 302 ( 18%) Throttle 20 240 ( 14%) Throttle 21 182 ( 11%) Throttle 22 120 ( 7%) Throttle 23 62 ( 3%) Throttle
I take that as switching between C0 and Cn to moulate performance, which is not as good as hardware-controlled because it is done over some clock periods and hardware-controlled is on 1 clock period. I suppose throttle states is not longer needed because I can adjust the idle promote/demote thresholds so that cores can just stay at Cn as long as possible to save power, there is not need to designate some duty cycles between C0 and Cn. Besides, from what I could find there are only 8 or 16 throttle states available on Intel processors, it's not so flexible.
I don't bother with throttle states anymore. HWiNFO gives 100% on ODCM no matter throttle states is allowed or not. Modern processors maybe only using throttle states for thermal control.
@mbk1969 I have been thinking about task scheduling on heterogeneous architectures like alder lake, snapdragon 8cx and future ryzen 8000 in preparation. Could dpc be routed to e-cores only? I know isr at most could be routed to cpu0 or cpu1 only, but I am not sure if dpc would wake up p-cores frequently while they are supposed to sleep most of the time. Is there any software that can track how long a thread runs? Windows 11 allows specifying a runtime threshold to move threads from one core architecture to another.
