Windows: Line-Based vs. Message Signaled-Based Interrupts. MSI tool.

You can always check whether any USB device is connected to (any) USB controller and then disable it if none (maybe even in BIOS).

Also I can assume that your NIC will not benefit from utilising multiple IRQs, so you can test it with the limit set to "1".

 

I want to spend tomorrow refactoring the code of v3 utility and then to freeze the development.
(Then I want to try to prototype a v4 - to do all the job without registry readings, just by using the Setup API.)
(Then maybe I will try to implement another utility - the cleanup utility for devices` leftovers in PNP registry keys.)

 

This is the PCIE 3.2 Gen 2 controller, each of the available ports has a dedicated controller for high bandwidth but is on the same bus.

 

Thank you for V3 !

 

http://www.mediafire.com/file/ewpy1p0rr132thk/MSI_util_v3.zip/file
MD5 hash for zip-file: DC46BBB8CA57B722D0CA1BF38F110683

Just code refactoring and small optimizations. I think I will stop with this version.

 

I have to keep HAGS ON no matter what cause it gives me significant performance boost in many games. DX12, vulkan for example.

 

That is the first report I have seen claiming a boost with HAG, how much are we talking off vers on?

 

Does it even affect DX12 and then Vulkan as well?
Eh I should look that up, thought these API's had greater control over this directly and this early scheduling hardware GPU support ... thingie .. mostly aided D3D11 and even then it's margin of error on most systems but I don't know what it'd look like with a non-standard not that users would regularly pair a very weak outdated CPU with a new state of the art GPU to make a CPU bottleneck of the biggest possible kind ever where this might show a bit bigger gains.

EDIT: Well it might but it's not likely to be a noticeable performance difference as per the Microsoft blog post.

Which would have been nice to have had a bit before every single article on the internet made it the GPU memory management toggle due to how often that got mentioned.
Makes it hard to find good info too because there's the MS blog post about it and then everything else on it as a memory manager.

https://devblogs.microsoft.com/directx/hardware-accelerated-gpu-scheduling/

"It shifts like one thread from the CPU to the GPU."

Developers got good at working with that but now this shift is probably going to cause a few compatibility issues for a while and Microsoft is working on some further improvements for later on where a bigger difference could be observed when this is enabled.

HAGS
Ah that's such a odd acronym but it's what it is.

 

Found some low level details in Intel documents:

10.11 MESSAGE SIGNALLED INTERRUPTS

The PCI Local Bus Specification, Rev 2.2 (www.pcisig.com) introduces the concept of message signalled interrupts.
As the specification indicates:

“Message signalled interrupts (MSI) is an optional feature that enables PCI devices to request service by writing a system-specified message to a system-specified address (PCI DWORD memory write transaction). The transaction address specifies the message destination while the transaction data specifies the message. System software is expected to initialize the message destination and message during device configuration, allocating one or more non-shared messages to each MSI capable function.” ​

The capabilities mechanism provided by the PCI Local Bus Specification is used to identify and configure MSI capable PCI devices. Among other fields, this structure contains a Message Data Register and a Message Address Register. To request service, the PCI device function writes the contents of the Message Data Register to the address contained in the Message Address Register (and the Message Upper Address register for 64-bit message addresses).
Section 10.11.1 and Section 10.11.2 provide layout details for the Message Address Register and the Message Data Register. The operation issued by the device is a PCI write command to the Message Address Register with the Message Data Register contents. The operation follows semantic rules as defined for PCI write operations and is a DWORD operation.

10.11.1 Message Address Register Format

Fields in the Message Address Register are as follows:
1. Bits 31-20 — These bits contain a fixed value for interrupt messages (0FEEH). This value locates interrupts at the 1-MByte area with a base address of 4G – 18M. All accesses to this region are directed as interrupt messages. Care must to be taken to ensure that no other device claims the region as I/O space.
2. Destination ID — This field contains an 8-bit destination ID. It identifies the message’s target processor(s). The destination ID corresponds to bits 63:56 of the I/O APIC Redirection Table Entry if the IOAPIC is used to dispatch the interrupt to the processor(s).
3. Redirection hint indication (RH) — When this bit is set, the message is directed to the processor with the lowest interrupt priority among processors that can receive the interrupt.

• When RH is 0, the interrupt is directed to the processor listed in the Destination ID field.
• When RH is 1 and the physical destination mode is used, the Destination ID field must not be set to FFH; it must point to a processor that is present and enabled to receive the interrupt.
• When RH is 1 and the logical destination mode is active in a system using a flat addressing model, the Destination ID field must be set so that bits set to 1 identify processors that are present and enabled to receive the interrupt.
• If RH is set to 1 and the logical destination mode is active in a system using cluster addressing model, then Destination ID field must not be set to FFH; the processors identified with this field must be present and enabled to receive the interrupt. ​

4. Destination mode (DM) — This bit indicates whether the Destination ID field should be interpreted as logical or physical APIC ID for delivery of the lowest priority interrupt.

• If RH is 1 and DM is 0, the Destination ID field is in physical destination mode and only the processor in the system that has the matching APIC ID is considered for delivery of that interrupt (this means no redirection).
• If RH is 1 and DM is 1, the Destination ID Field is interpreted as in logical destination mode and the redirection is limited to only those processors that are part of the logical group of processors based on the processor’s logical APIC ID and the Destination ID field in the message. The logical group of processors consists of those identified by matching the 8-bit Destination ID with the logical destination identified by the Destination Format Register and the Logical Destination Register in each local APIC. The details are similar to those described in Section 10.6.2, “Determining IPI Destination.”
• If RH is 0, then the DM bit is ignored and the message is sent ahead independent of whether the physical or logical destination mode is used.​

10.11.2 Message Data Register Format

Reserved fields are not assumed to be any value. Software must preserve their contents on writes. Other fields in the Message Data Register are described below.
1. Vector — This 8-bit field contains the interrupt vector associated with the message. Values range from 010H to 0FEH. Software must guarantee that the field is not programmed with vector 00H to 0FH.
2. Delivery Mode — This 3-bit field specifies how the interrupt receipt is handled. Delivery Modes operate only in conjunction with specified Trigger Modes. Correct Trigger Modes must be guaranteed by software. Restrictions are indicated below:

a. 000B (Fixed Mode) — Deliver the signal to all the agents listed in the destination. The Trigger Mode for fixed delivery mode can be edge or level.
b. 001B (Lowest Priority) — Deliver the signal to the agent that is executing at the lowest priority of all agents listed in the destination field. The trigger mode can be edge or level.
c. 010B (System Management Interrupt or SMI) — The delivery mode is edge only. For systems that rely on SMI semantics, the vector field is ignored but must be programmed to all zeroes for future compatibility.
d. 100B (NMI) — Deliver the signal to all the agents listed in the destination field. The vector information is ignored. NMI is an edge triggered interrupt regardless of the Trigger Mode Setting.
e. 101B (INIT) — Deliver this signal to all the agents listed in the destination field. The vector information is ignored. INIT is an edge triggered interrupt regardless of the Trigger Mode Setting.
f. 111B (ExtINT) — Deliver the signal to the INTR signal of all agents in the destination field (as an interrupt that originated from an 8259A compatible interrupt controller). The vector is supplied by the INTA cycle issued by the activation of the ExtINT. ExtINT is an edge triggered interrupt.​

3. Level — Edge triggered interrupt messages are always interpreted as assert messages. For edge triggered interrupts this field is not used. For level triggered interrupts, this bit reflects the state of the interrupt input.
4. Trigger Mode — This field indicates the signal type that will trigger a message.

a. 0 — Indicates edge sensitive.
b. 1 — Indicates level sensitive.​

 

Hi, some weeks ago I was asked to test the msi vs line based interrupt, and more importantly the "Interrupt priorities".

After a whole week of testing and latency monitoring under LatencyMon, here are my conclusions :
- First there is a definitive/real difference in Latency DPC and IRS when priorities are set. This is not useless, and definitely affect windows and DPC spikes.

- Negative impact is more frequent than positive impact. Setting the Built in Audio card to anything creates DPC spikes. I experimented by setting most of the USB Drivers / SATA / I2C to LOW, and setting GPU and Audio to HIGH. Created bigger latency spikes (before=80-150us After=250-400us). This came only from setting priorities !!! Be careful.

- It's better to not set priorities for most devices. Letting the os executing interrupts as they come is most of the time the best way to do it (in my tests). Setting priorities to HIGH has a negative effect most of the time. The less the priorities are set, the better !

- The only tweak I recommend is setting the Sata AHCI driver priority to Low. It's the only tweak that made a positive difference (less frequent spikes).

- On my laptop (low power 1GHZ 2cores/4threads) setting the Built in Audio to use legacy Line based mode, lowers the steady latency (Lowest current reading latencyMon) from ranging 15-30us in msi, to a lower 9-30us in Line based mode. I can't explain this.

Now I have only GPU at High and SATA to low, I am still testing to see if I recommend or if it does make substantial difference.

I hope it help you mbk1969 and you guys also. Please post your finding to see if my conclusions are valid.

I have ntoskrnl.exe spikes at 150us I can't get rid off. If you know what process affect ntoskrnl It would be welcome. I need help on this ! Could it be possible it's because of my low power CPU ?

 

Since ntoskrnl.exe is a part of Windows kernel it is affected by all processes - they all call the Win API functions which are dispatched to kernel.

PS But I was hoping not for LatencyMon sessions, but for your real time audio tasks. LatencyMon is not fully reliable app (it has bugs/glitches on my several rigs). Fluent or glitchy work of your tasks is much more interesting.

 

if you want to drop ntoskrnl you must disable all cpu C states and keep the cpu fully awake and unpacked at all times.

 

Sorry mbk1969, I did not understand, but the settings are still on. I will try record in real-time with my audio interface and see if the conclusion still hold hold up.
I also have a mix I need to finish, I will do it with the priorities set and see if there is a difference in the amount of plugins I can load while mixing audio in real-time (ASIO mode 64samples).
That true we rely too much on bench sometimes when we use our laptops completely differently than a bench.

Astyanax I did this, I disabled everything the CPU run at a steady 1GHZ all the time, I even disabled power saving features in the PCH like, bi-directional Prochot, SA Geyserville and also PCI express powersaving features and ASPM.
I only kept "PCI clock gating" I will disable it and see if it makes a difference (and also hyperthreading, I will also disable).

On my desktop I can Idle with no bars in Latencymon (12cores cpu a 3GHZ)
But my laptop is only a dualcore at 1GHz, so I thought it was because it can't handle "windows task" fast enough ?

 

@vigan1

Have you seen my private messages (sent on this forum)?

 

No I just saw them. This is doable !

 

I have a few questions. Should I put my Intel PCIE controller on msi mode because I see a lot of people have their's on msi mode but mine doesn't say its supported. And what is Intel Gaussian Mixture Model and Intel Thermal Subsystem and what values should I put for those?

 

I would not touch Intel PCIe controller.

 

But what is the other stuff and what does it do? And should I put it on low priority?

 

Other stuff you can switch to MSI mode. Do not touch priority, it is not clear how that affects system.

 

Since High Definition Audio Controllers share IRQ (16, 17) with another devices you better switch them to MSI mode.