Windows: Line-Based vs. Message Signaled-Based Interrupts. MSI tool.

Discussion in 'Operating Systems' started by mbk1969, May 7, 2013.

  1. Astyanax

    Astyanax Ancient Guru

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    irq sharing isn't a problem with any irq over 24, these are all virtualized at this point and ioapic via MSI/MSI-X.
     
  2. mbk1969

    mbk1969 Ancient Guru

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    That's on hardware/firmware level. But for drivers of devices which share IRQ there is no difference whether IRQ virtualized or not - they should ask (back) their devices to confirm that interrupt arrived from their device.
     
    Last edited: Dec 10, 2018
  3. pipes

    pipes Member Guru

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    io use a 5960x with 40 line
     
  4. mbk1969

    mbk1969 Ancient Guru

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    And exact model of motherboard?
     

  5. limeay

    limeay Active Member

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    Hi, mbk1969

    I have ton of extra questions. Please to everyone who reads this... dont get mad because my questions irritate or get your brain to hurt because my brain is confused too so to why microsoft does things in this manner... they should of just renamed msi-x to something else so we cant screw that up because some people call msi-x -> msi... it's not to be interchanged so lightly...

    This is funny because I was just thinking about how my ar8151 doesn't enable msi-x when I press the check button for my notebook but works for my mobo g1 sniper m5 ar8161.
    P.S: you already replied to this question just a heads up though.

    Questions are:
    1. This new msi utility v2 has right hand column supported modes... line, msi, msix.
    How do you know if you're using intX, msi or msi-x?
    Like definitely tell.

    2. What do these registries actually mean?

    [Msi.Addreg]
    HKR, "Interrupt Management", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MSISupported, 0x00010001, 0
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MessageNumberLimit, 0x00010001, 1

    [MsiX.Addreg]
    HKR, "Interrupt Management", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MSISupported, 0x00010001, 0

    https://www.ath-drivers.eu/64bit-inf-file-version-2.1.0.27-with-id-502.html

    Reason why I ask this is because remember my old complaint? Killer networking said enabling msi-x caused the drivers to bog down connection speed from 250mbps to 90mbps I believe, please reread my other posts if confused :S I was wondering maybe when they say enable MSI it actually enables the older msi and not msi-X maybe that was why it caused him problems? Because even another coworker of theirs said that it was defaulted msi-x I forget where to find this before i emailed killer... but

    3. From question TWO, if you'd read that it says msi-x is set to 0 in drivers but for regular msi it's set to 1?

    [mydevice.HW]
    AddReg = mydevice_addreg

    [mydevice_addreg]
    HKR,Interrupt Management,,0x00000010
    HKR,Interrupt Management\MessageSignaledInterruptProperties,,0x00000010
    HKR,Interrupt Management\MessageSignaledInterruptProperties,MSISupported,0x00010001,1

    https://docs.microsoft.com/en-us/wi...g-message-signaled-interrupts-in-the-registry

    This link just tells you msi how to enable and its dates from 2017 so it should saying msi-x but man I wish these topics were extremely specific. They would label the topic "enabling messaged signaled interrupts X in the registry" instead so no confusions. I'm going to try and look into this with killernetworkings inf file and see what's the difference if I have time. I want to see if there is any difference to what we do with this little tweak. I'm starting to go crazy and dont know whats up or down now and I need to get my rationality back in order... sometimes people put stuff out there and it's completely wrong and also my knowledge or coding and so forth is p*ss poor lol but gonna give it the ole wrangle dangle or w/e :)

    4. What I'd like to know is can you code your program to where it'll descriptively tell the user of the program on what that certain device's support mode that is enabled?

    5. Obviouslytriggered says it's on by default & apparently what we're doing is snake oil. I really need to understand what the .information for msi-x and msi differences are... Are they like the one I mentioned above? ^ https://www.google.com/amp/s/amp.re..._no_more_complete_test_on_how/#ampf=undefined

    6. Why haven't you updated your msi utility peogram through your github?https://github.com/CHEF-KOCH/MSI-utility
     
    Last edited: Dec 16, 2018
  6. mbk1969

    mbk1969 Ancient Guru

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    There is no way for us mere mortals to distinct MSI and MSI-X modes. And this is not a big difference as it would with Line-based and MSI modes.
    MSI mode was introduced for PCI v2.2 (old PCI not PCI-Express). PCI v3 introduced improvement for MSI which was called MSI-X (and again - old PCI bus).
    Here are the differences between MSI and MSI-X (from Wikipedia):
    So the differences are:
    - increased number of messages per device in MSI-X;
    - unique address per each message for MSI-X instead of single address per all messages for MSI.


    HKR, "Interrupt Management", 0x00000010 - registry key "Interrupt Management".
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", 0x00000010 - registry key "MessageSignaledInterruptProperties".
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MSISupported, 0x00010001, 0 - registry value "MSISupported" of type DWORD with value "0".
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MessageNumberLimit, 0x00010001, 1 - registry value "MessageNumberLimit" of type DWORD with value "1"


    No.

    Obviouslytriggered doesn`t understand what he is talking about.

    That`s not my utility. That`s my old PowerShell script re-worked by Chef Koch.


    PS You are worried too much with this "MSI vs MSI-X" thing.
     
    Last edited: Dec 16, 2018
  7. limeay

    limeay Active Member

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    Yes I am worrying too much. I really dont know why the registry key itself says MSI addreg and msix addreg now... I've tried looking into Microsoft's site... pretty much anytime they add a function to registry or cmd they list what it does... so maybe I guess I am wrong. I was thinking this is more complicated than what it is from reading inf file.

    Alright, i guess i understand this now, i messed up and read the messagenumber limit line at 1 and the bottom msix addreg 3rd line is msisupported... >_< lol Thought 1 was for msi and 0 was for msix

    [Msi.Addreg]
    HKR, "Interrupt Management", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MSISupported, 0x00010001, 0
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MessageNumberLimit, 0x00010001, 1

    [MsiX.Addreg]
    HKR, "Interrupt Management", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MSISupported, 0x00010001, 0

    Also would you know if when they say 2048 interrupts for a device, is that for each device or a total interrupts for all your devices

    After someone explains this I think I'm out of questions and most likely content. I'm sorry for confusing those out there.

    P.S extremely stupid on Microsoft's eyes they have two different MSI & MSI-X can be enabled using the same 1 registry edit and you can't even tell if it'll bottle neck your system or not.
     
    Last edited: Dec 17, 2018
  8. limeay

    limeay Active Member

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    4. What I'd like to know is can you code your program to where it'll descriptively tell the user of the program on what that certain device's support mode that is enabled?
    There is no way for us mere mortals to distinct MSI and MSI-X modes. And this is not a big difference as it would with Line-based and MSI modes.
    MSI mode was introduced for PCI v2.2 (old PCI not PCI-Express). PCI v3 introduced improvement for MSI which was called MSI-X (and again - old PCI bus).
    Here are the differences between MSI and MSI-X (from Wikipedia):

    Okay, i was wondering on that. How'd you code this program to where it can tell which supported modes each device can use? Only my Qualcomm Atheros AR8161 can support all 3 modes.

    Also, figured out that my killer networking drivers inf is like this:
    e2xw10x64.inf file from C:\Users\Lime\Downloads\Production\Windows10-x64\Eth

    [Msi.Addreg]
    HKR, "Interrupt Management", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MSISupported, 0x00010001, 0
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MessageNumberLimit, 0x00010001, 1

    [MsiX.Addreg]
    HKR, "Interrupt Management", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MSISupported, 0x00010001, 0

    Not going to lie but i see no difference in the .inf, hmm...Pretty much means they were not enabled by default... eh...

    This is the code from microsoft
    [mydevice.HW]
    AddReg = mydevice_addreg

    [mydevice_addreg]
    HKR,Interrupt Management,,0x00000010
    HKR,Interrupt Management\MessageSignaledInterruptProperties,,0x00000010
    HKR,Interrupt Management\MessageSignaledInterruptProperties,MSISupported,0x00010001,1
    https://docs.microsoft.com/en-us/wi...g-message-signaled-interrupts-in-the-registry
     
    Last edited: Dec 17, 2018
  9. mbk1969

    mbk1969 Ancient Guru

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    2048 messages per one device (2048 messages for each device working in MSI-X mode).


    Code just receives the flags of supported modes. There are no flags of actual current mode.


    Copy full text of the inf-file for your Killer NIC and paste it here under the spoiler tags.
     
  10. limeay

    limeay Active Member

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    Erm, i think you misunderstood what i meant, sorry if i said it wrong, you said there are no flags of actual current mode... did you mean that it just labels a device with just supported modes but some devices don't get that same treatment. Kinda lost what you mean on this.
     

  11. limeay

    limeay Active Member

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    KILLER E2201 NIC builtin V9.0.0.48 8/31/2018

    Code:
    ;*****************************************************************************
    ;*
    ;*  E2xw8x64.INF  -  Killer E2X00 Series PCI-E Ethernet Controller
    ;*  Copyright 2015 - Rivet Networks, LLC.
    ;*
    ;*  INF File for NDIS Miniport Driver for Windows 10 x64
    ;*
    ;*****************************************************************************
    [Version]
    Signature   = "$Windows NT$"
    Class       = Net
    ClassGUID   = {4d36e972-e325-11ce-bfc1-08002be10318}
    Provider    = %RIVET%
    CatalogFile = e2XW10x64.cat
    DriverVer=08/31/2018,9.0.0.48
    
    [Manufacturer]
    %RIVET% = Rivet, NTamd64.6.3
    
    [ControlFlags]
    
    ExcludeFromSelect    = *
    
    
    [Rivet.NTamd64.6.3]
    ; DisplayName           Section                DeviceID
    ; -----------           -------                   --------
    ; E2X Hardware
    %RIVET.L1F.E22%  =          RIVET.ndi,             PCI\VEN_1969&DEV_E091
    %RIVET.L1F.E24%  =          RIVET.ndi,             PCI\VEN_1969&DEV_E0A1
    %RIVET.L1F.E25%  =          RIVET.ndi,             PCI\VEN_1969&DEV_E0B1
    
    ; Vendor Specific
    %RIVET.L1F.E24%  =          RIVET.ndi,             PCI\VEN_1969&DEV_E0A1&SUBSYS_10511025  ;Mustang
    %RIVET.L1F.E24%  =          RIVET.ndi,             PCI\VEN_1969&DEV_E0A1&SUBSYS_105B1025  ;Challenger
    %RIVET.L1F.E24%  =          RIVET.ndi,             PCI\VEN_1969&DEV_E0A1&SUBSYS_380217AA  ;Lenovo
    ; ..............................................................................
    
    [RIVET.ndi]
    Characteristics = 0x84      ; NCF_HAS_UI | NCF_PHYSICAL
    BusType         = 5         ;PCI
    DelReg          = Del.reg, EEELPI.Delreg
    AddReg          = L1C.reg, L1C.params, Common.params, ShutOn.params, WOLDefault.params, PM.params, RSS.params, Intr.params, EEELPI.params, Ecma.params
    CopyFiles       = L1C.CopyFiles
    *IfType         = 6        ; IF_TYPE_ETHERNET_CSMACD
    *MediaType      = 0        ; NdisMedium802_3
    *PhysicalMediaType = 14     ; NdisPhysicalMedium802_3
    
    [RIVET.ndi.Hw]
    Include = machine.inf
    Needs = PciASPMOptIn.Hw
    Addreg = MsiX.Addreg
    
    [RIVET.ndi.Services]
    AddService = e2xw10x64, 2,  RL1C.Service, L1C.EventLog
    ;-----------------------------------------------------------------------------
    ; L1C  specific
    ;
    [L1C.reg]
    HKR, Ndi, Service,    0, "e2xw10x64"
    ; use ndis5 as the upper bound because NT supports it
    HKR, Ndi\Interfaces, UpperRange, 0, "ndis5"
    HKR, Ndi\Interfaces, LowerRange, 0, "ethernet"
    
    [Msi.Addreg]
    HKR, "Interrupt Management", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MSISupported, 0x00010001, 0
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MessageNumberLimit, 0x00010001, 1
    
    [MsiX.Addreg]
    HKR, "Interrupt Management", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", 0x00000010
    HKR, "Interrupt Management\MessageSignaledInterruptProperties", MSISupported, 0x00010001, 0
    
    [Del.reg]
    HKR, Ndi\Params\WakeUpCapabilities
    HKR, Ndi\Params\ShutdownWake
    ;HKR, Ndi\Params\*RSS
    ;HKR, Ndi\Params\*NumRssQueues
    
    [EEELPI.Delreg]
    HKR, Ndi\Params\EEESupported
    
    [RL1C.Service]
    DisplayName     = %RIVET.Service.DispName%
    ServiceType     = 1 ;%SERVICE_KERNEL_DRIVER%
    StartType       = 3 ;%SERVICE_DEMAND_START%
    ErrorControl    = 1 ;%SERVICE_ERROR_NORMAL%
    ServiceBinary   = %12%\e2xw10x64.sys
    LoadOrderGroup  = NDIS
    
    [L1C.EventLog]
    AddReg = L1C.AddEventLog.reg
    
    [L1C.AddEventLog.reg]
    HKR,, EventMessageFile,    0x00020000, "%%SystemRoot%%\System32\Drivers\e2xw10x64.sys"
    HKR,, TypesSupported,    0x00010001, 7
    
    [Toshiba.params]
    HKR,, WOLMode,            0x00010001, 1
    
    [ToPatch.params]
    HKR,, ToPatch,            0x00010001, 1
    
    [PWMNone.params]
    HKR,, PnPCapabilities,    0x00010001, 0x0038
    
    [PWM.params]
    HKR,, PnPCapabilities,    0x00010001, 0x0020
    
    [PWMAll.params]
    HKR,, PnPCapabilities,    0x00010001, 0x0120
    
    [ASPM1M.params]
    HKR,, ASPMLim,            0x00010001, 1
    
    [ASPM10M.params]
    HKR,, ASPMLim,            0x00010001, 2
    
    [ASPM100M.params]
    HKR,, ASPMLim,            0x00010001, 3
    
    [LongCable.params]
    HKR,, LongCable,        0x00010001, 1
    
    [TxPerf.params]
    HKR,, TxPerf,           0x00010001, 1
    
    [Intr.params]
    HKR,, MSIX,                    0x00010001, 1
    
    [L1C.params]
    HKR, Ndi\Params\*JumboPacket,                ParamDesc,      0,      %JumboFrame%
    HKR, Ndi\Params\*JumboPacket,                default,        0,      "1514"
    HKR, Ndi\Params\*JumboPacket,                type,          0,      "enum"
    HKR, Ndi\Params\*JumboPacket\enum,          "1514",        0,      %Disabled%
    HKR, Ndi\Params\*JumboPacket\enum,          "2048",        0,      %2KBMTU%
    HKR, Ndi\Params\*JumboPacket\enum,          "3072",        0,      %3KBMTU%
    HKR, Ndi\Params\*JumboPacket\enum,          "4096",        0,      %4KBMTU%
    HKR, Ndi\Params\*JumboPacket\enum,          "5120",        0,      %5KBMTU%
    HKR, Ndi\Params\*JumboPacket\enum,          "6144",        0,      %6KBMTU%
    HKR, Ndi\Params\*JumboPacket\enum,          "7168",        0,      %7KBMTU%
    HKR, Ndi\params\*JumboPacket\enum,          "8192",        0,     %8KBMTU%
    HKR, Ndi\params\*JumboPacket\enum,          "9216",        0,     %9KBMTU%
    
    [ExRSS.params]
    HKR, Ndi\Params\RSS,                ParamDesc,    0,    %RSS%
    HKR, Ndi\Params\RSS,                Type,        0,    "enum"
    HKR, Ndi\Params\RSS\enum,            1,        0,    %Enabled%
    HKR, Ndi\Params\RSS\enum,            0,        0,    %Disabled%
    HKR, Ndi\Params\RSS,                Default,    0,    "0"
    
    [RSS.params]
    ;HKR, Ndi\Params\RSS,                ParamDesc,    0,    %RSS%
    ;HKR, Ndi\Params\RSS,                Type,        0,    "enum"
    ;HKR, Ndi\Params\RSS\enum,            1,        0,    %Enabled%
    ;HKR, Ndi\Params\RSS\enum,            0,        0,    %Disabled%
    ;HKR, Ndi\Params\RSS,                Default,    0,    "1"
    
    ;HKR, Ndi\Params\NumRssQueues,            ParamDesc,    0,    %RssQs%
    ;HKR, Ndi\Params\NumRssQueues,            Type,        0,    "enum"
    ;HKR, Ndi\Params\NumRssQueues\enum,        "4",        0,    "4 RSS Queues"
    ;HKR, Ndi\Params\NumRssQueues\enum,        "2",        0,    "2 RSS Queues"
    ;HKR, Ndi\Params\NumRssQueues\enum,        "1",        0,    "1 RSS Queues"
    ;HKR, Ndi\Params\NumRssQueues,            Default,    0,    "2"
    
    HKR, Ndi\Params\*RSS,                ParamDesc,    0,    %RSS%
    HKR, Ndi\Params\*RSS,                Type,        0,    "enum"
    HKR, Ndi\Params\*RSS\enum,            1,        0,    %Enabled%
    HKR, Ndi\Params\*RSS\enum,            0,        0,    %Disabled%
    HKR, Ndi\Params\*RSS,                Default,    0,    "1"
    
    HKR, Ndi\Params\*NumRssQueues,            ParamDesc,    0,    %RssQs%
    HKR, Ndi\Params\*NumRssQueues,            Type,        0,    "enum"
    ;HKR, Ndi\Params\*NumRssQueues\enum,        "8",        0,    "8 RSS Queues"
    ;HKR, Ndi\Params\*NumRssQueues\enum,        "6",        0,    "6 RSS Queues"
    HKR, Ndi\Params\*NumRssQueues\enum,        "4",        0,    "4 RSS Queues"
    HKR, Ndi\Params\*NumRssQueues\enum,        "2",        0,    "2 RSS Queues"
    HKR, Ndi\Params\*NumRssQueues\enum,        "1",        0,    "1 RSS Queues"
    HKR, Ndi\Params\*NumRssQueues,            Default,    0,    "2"
    
    [L2CB.params]
    HKR, Ndi\Params\APSmode,                        ParamDesc,      0,      %APSmode%
    HKR, Ndi\Params\APSmode,                        Type,           0,      "enum"
    HKR, Ndi\Params\APSmode\enum,                     "1",            0,      %Enabled%
    HKR, Ndi\Params\APSmode\enum,                     "0",            0,      %Disabled%
    HKR, Ndi\Params\APSmode,                        Default,        0,      "0"
    ;-----------------------------------------------------------------------------
    
    [Ecma.params]
    HKR, Ndi\Params\Ecma,                        ParamDesc,      0,      %ECMA%
    HKR, Ndi\Params\Ecma,                        Type,           0,      "enum"
    HKR, Ndi\Params\Ecma\enum,                     "1",            0,      %Enabled%
    HKR, Ndi\Params\Ecma\enum,                     "0",            0,      %Disabled%
    HKR, Ndi\Params\Ecma,                        Default,        0,      "0"
    
    ;-----------------------------------------------------------------------------
    ;
    [Common.params]
    HKR, Ndi\Params\MaxInterrupt,            ParamDesc,    0,    %MaxIrq%
    HKR, Ndi\Params\MaxInterrupt,            Type,        0,    "int"
    HKR, Ndi\Params\MaxInterrupt,            Base,        0,    "10"
    HKR, Ndi\Params\MaxInterrupt,            Min,        0,    "1000"
    HKR, Ndi\Params\MaxInterrupt,            Max,        0,    "30000"
    HKR, Ndi\Params\MaxInterrupt,            Step,        0,    "500"
    HKR, Ndi\Params\MaxInterrupt,            Default,    0,    "10000"
    
    HKR, Ndi\Params\*SpeedDuplex,            ParamDesc,    0,    %SpeedDuplex%
    HKR, Ndi\Params\*SpeedDuplex,            Type,        0,    "enum"
    HKR, Ndi\Params\*SpeedDuplex,            Default,    0,    "0"
    HKR, Ndi\Params\*SpeedDuplex\enum,         "0",        0,    %Auto%
    HKR, Ndi\Params\*SpeedDuplex\enum,         "1",        0,    %10MHD%
    HKR, Ndi\Params\*SpeedDuplex\enum,         "2",        0,    %10MFD%
    HKR, Ndi\Params\*SpeedDuplex\enum,         "3",        0,    %100MHD%
    HKR, Ndi\Params\*SpeedDuplex\enum,         "4",        0,    %100MFD%
    
    HKR, Ndi\Params\*ReceiveBuffers,        ParamDesc,    0,      %ReceiveBuffers%
    HKR, Ndi\Params\*ReceiveBuffers,        Type,        0,      "int"
    HKR, Ndi\Params\*ReceiveBuffers,        Base,        0,      "10"
    HKR, Ndi\Params\*ReceiveBuffers,        Min,        0,      "16"
    HKR, Ndi\Params\*ReceiveBuffers,        Max,        0,      "2048"
    HKR, Ndi\Params\*ReceiveBuffers,        Step,        0,      "16"
    HKR, Ndi\Params\*ReceiveBuffers,        Default,    0,      "1024"
    
    HKR, Ndi\Params\*TransmitBuffers,        ParamDesc,    0,      %TransmitBuffers%
    HKR, Ndi\Params\*TransmitBuffers,        Type,        0,      "int"
    HKR, Ndi\Params\*TransmitBuffers,        Base,        0,      "10"
    HKR, Ndi\Params\*TransmitBuffers,        Min,        0,      "16"
    HKR, Ndi\Params\*TransmitBuffers,        Max,        0,      "1024"
    HKR, Ndi\Params\*TransmitBuffers,        Step,        0,      "16"
    HKR, Ndi\Params\*TransmitBuffers,        Default,    0,      "1024"
    
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4,    ParamDesc,    0,     %TCPChksumOffv4%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4,    Type,        0,     "enum"
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum,    "3",        0,     %TXRXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum,    "2",        0,     %RXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum,    "1",        0,     %TXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum,    "0",        0,     %Disabled%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4,    Default,    0,     "3"
    
    HKR, Ndi\Params\*IPChecksumOffloadIPv4,        ParamDesc,    0,     %IPChksumOffv4%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4,        Type,        0,     "enum"
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum,    "3",        0,     %TXRXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum,    "2",        0,     %RXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum,    "1",        0,     %TXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum,    "0",        0,     %Disabled%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4,        Default,    0,     "3"
    
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4,    ParamDesc,    0,     %UDPChksumOffv4%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4,    Type,        0,     "enum"
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum,    "3",        0,     %TXRXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum,    "2",        0,     %RXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum,    "1",        0,     %TXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum,    "0",        0,     %Disabled%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4,    Default,    0,     "3"
     
  12. limeay

    limeay Active Member

    Messages:
    60
    Likes Received:
    1
    GPU:
    Nvidia GTX 1080 Ti
    Code:
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, ParamDesc, 0, %TCPChksumOffv6%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, Type, 0, "enum"
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, Default, 0, "3"
    
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, ParamDesc, 0, %UDPChksumOffv6%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, Type, 0, "enum"
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, Default, 0, "3"
    
    HKR, Ndi\Params\*LsoV1IPv4, ParamDesc, 0, %LSOv1IPv4%
    HKR, Ndi\Params\*LsoV1IPv4, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV1IPv4\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV1IPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV1IPv4, Default, 0, "1"
    
    HKR, Ndi\Params\*LsoV2IPv4, ParamDesc, 0, %LSOv2IPv4%
    HKR, Ndi\Params\*LsoV2IPv4, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV2IPv4\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV2IPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV2IPv4, Default, 0, "1"
    
    HKR, Ndi\Params\*LsoV2IPv6, ParamDesc, 0, %LSOv2IPv6%
    HKR, Ndi\Params\*LsoV2IPv6, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV2IPv6\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV2IPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV2IPv6, Default, 0, "1"
    
    HKR, Ndi\Params\NetworkAddress, ParamDesc, 0, %NetAddress%
    HKR, Ndi\Params\NetworkAddress, Type, 0, "edit"
    HKR, Ndi\Params\NetworkAddress, LimitText, 0, "12"
    HKR, Ndi\Params\NetworkAddress, UpperCase, 0, "1"
    HKR, Ndi\Params\NetworkAddress, Default, 0, ""
    HKR, Ndi\Params\NetworkAddress, Optional, 0, "1"
    
    HKR, Ndi\Params\*InterruptModeration, ParamDesc, 0, %IntMod%
    HKR, Ndi\Params\*InterruptModeration, Type, 0, "enum"
    HKR, Ndi\Params\*InterruptModeration\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*InterruptModeration\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*InterruptModeration, Default, 0, "1"
    
    HKR, Ndi\Params\*FlowControl, ParamDesc, 0, %FlowCtrl%
    HKR, Ndi\Params\*FlowControl, Type, 0, "enum"
    HKR, Ndi\Params\*FlowControl\Enum, "1", 0, %TxEna%
    HKR, Ndi\Params\*FlowControl\Enum, "2", 0, %RxEna%
    HKR, Ndi\Params\*FlowControl\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*FlowControl\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*FlowControl, Default, 0, "3"
    
    HKR, Ndi\Params\VLanID, ParamDesc, 0, %VLanID%
    HKR, Ndi\Params\VLanID, Type, 0, "long"
    HKR, Ndi\Params\VLanID, Base, 0, "10"
    HKR, Ndi\Params\VLanID, Min, 0, "0"
    HKR, Ndi\Params\VLanID, Max, 0, "4094"
    HKR, Ndi\Params\VLanID, Step, 0, "1"
    HKR, Ndi\Params\VLanID, Default, 0, "0"
    
    HKR, Ndi\Params\Ioac_SwoiSupported, ParamDesc, 0, %SWOI%
    HKR, Ndi\Params\Ioac_SwoiSupported, Type, 0, "enum"
    HKR, Ndi\Params\Ioac_SwoiSupported\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\Ioac_SwoiSupported\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\Ioac_SwoiSupported, Default, 0, "0"
    
    [Pega.params]
    HKR, Ndi\Params\MaxInterrupt, ParamDesc, 0, %MaxIrq%
    HKR, Ndi\Params\MaxInterrupt, Type, 0, "int"
    HKR, Ndi\Params\MaxInterrupt, Base, 0, "10"
    HKR, Ndi\Params\MaxInterrupt, Min, 0, "1000"
    HKR, Ndi\Params\MaxInterrupt, Max, 0, "30000"
    HKR, Ndi\Params\MaxInterrupt, Step, 0, "500"
    HKR, Ndi\Params\MaxInterrupt, Default, 0, "5000"
    
    HKR, Ndi\Params\*SpeedDuplex, ParamDesc, 0, %SpeedDuplex%
    HKR, Ndi\Params\*SpeedDuplex, Type, 0, "enum"
    HKR, Ndi\Params\*SpeedDuplex, Default, 0, "0"
    HKR, Ndi\Params\*SpeedDuplex\enum, "0", 0, %Auto%
    HKR, Ndi\Params\*SpeedDuplex\enum, "1", 0, %10MHD%
    HKR, Ndi\Params\*SpeedDuplex\enum, "2", 0, %10MFD%
    HKR, Ndi\Params\*SpeedDuplex\enum, "3", 0, %100MHD%
    HKR, Ndi\Params\*SpeedDuplex\enum, "4", 0, %100MFD%
    
    HKR, Ndi\Params\*ReceiveBuffers, ParamDesc, 0, %ReceiveBuffers%
    HKR, Ndi\Params\*ReceiveBuffers, Type, 0, "int"
    HKR, Ndi\Params\*ReceiveBuffers, Base, 0, "10"
    HKR, Ndi\Params\*ReceiveBuffers, Min, 0, "16"
    HKR, Ndi\Params\*ReceiveBuffers, Max, 0, "2048"
    HKR, Ndi\Params\*ReceiveBuffers, Step, 0, "16"
    HKR, Ndi\Params\*ReceiveBuffers, Default, 0, "1024"
    
    HKR, Ndi\Params\*TransmitBuffers, ParamDesc, 0, %TransmitBuffers%
    HKR, Ndi\Params\*TransmitBuffers, Type, 0, "int"
    HKR, Ndi\Params\*TransmitBuffers, Base, 0, "10"
    HKR, Ndi\Params\*TransmitBuffers, Min, 0, "16"
    HKR, Ndi\Params\*TransmitBuffers, Max, 0, "1024"
    HKR, Ndi\Params\*TransmitBuffers, Step, 0, "16"
    HKR, Ndi\Params\*TransmitBuffers, Default, 0, "256"
    
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4, ParamDesc, 0, %TCPChksumOffv4%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4, Type, 0, "enum"
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4, Default, 0, "3"
    
    HKR, Ndi\Params\*IPChecksumOffloadIPv4, ParamDesc, 0, %IPChksumOffv4%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4, Type, 0, "enum"
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4, Default, 0, "3"
    
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4, ParamDesc, 0, %UDPChksumOffv4%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4, Type, 0, "enum"
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4, Default, 0, "3"
    
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, ParamDesc, 0, %TCPChksumOffv6%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, Type, 0, "enum"
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, Default, 0, "3"
    
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, ParamDesc, 0, %UDPChksumOffv6%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, Type, 0, "enum"
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, Default, 0, "3"
    
    HKR, Ndi\Params\*LsoV1IPv4, ParamDesc, 0, %LSOv1IPv4%
    HKR, Ndi\Params\*LsoV1IPv4, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV1IPv4\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV1IPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV1IPv4, Default, 0, "1"
    
    HKR, Ndi\Params\*LsoV2IPv4, ParamDesc, 0, %LSOv2IPv4%
    HKR, Ndi\Params\*LsoV2IPv4, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV2IPv4\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV2IPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV2IPv4, Default, 0, "0"
    
    HKR, Ndi\Params\*LsoV2IPv6, ParamDesc, 0, %LSOv2IPv6%
    HKR, Ndi\Params\*LsoV2IPv6, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV2IPv6\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV2IPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV2IPv6, Default, 0, "0"
    
    HKR, Ndi\Params\NetworkAddress, ParamDesc, 0, %NetAddress%
    HKR, Ndi\Params\NetworkAddress, Type, 0, "edit"
    HKR, Ndi\Params\NetworkAddress, LimitText, 0, "12"
    HKR, Ndi\Params\NetworkAddress, UpperCase, 0, "1"
    HKR, Ndi\Params\NetworkAddress, Default, 0, ""
    HKR, Ndi\Params\NetworkAddress, Optional, 0, "1"
    
    HKR, Ndi\Params\*InterruptModeration, ParamDesc, 0, %IntMod%
    HKR, Ndi\Params\*InterruptModeration, Type, 0, "enum"
    HKR, Ndi\Params\*InterruptModeration\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*InterruptModeration\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*InterruptModeration, Default, 0, "1"
    
    HKR, Ndi\Params\*FlowControl, ParamDesc, 0, %FlowCtrl%
    HKR, Ndi\Params\*FlowControl, Type, 0, "enum"
    HKR, Ndi\Params\*FlowControl\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*FlowControl\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*FlowControl, Default, 0, "3"
    
    HKR, Ndi\Params\VLanID, ParamDesc, 0, %VLanID%
    HKR, Ndi\Params\VLanID, Type, 0, "long"
    HKR, Ndi\Params\VLanID, Base, 0, "10"
    HKR, Ndi\Params\VLanID, Min, 0, "0"
    HKR, Ndi\Params\VLanID, Max, 0, "4094"
    HKR, Ndi\Params\VLanID, Step, 0, "1"
    HKR, Ndi\Params\VLanID, Default, 0, "0"
    
    HKR, Ndi\Params\Ioac_SwoiSupported, ParamDesc, 0, %SWOI%
    HKR, Ndi\Params\Ioac_SwoiSupported, Type, 0, "enum"
    HKR, Ndi\Params\Ioac_SwoiSupported\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\Ioac_SwoiSupported\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\Ioac_SwoiSupported, Default, 0, "0"
    
    [FUJU.params]
    HKR, Ndi\Params\MaxInterrupt, ParamDesc, 0, %MaxIrq%
    HKR, Ndi\Params\MaxInterrupt, Type, 0, "int"
    HKR, Ndi\Params\MaxInterrupt, Base, 0, "10"
    HKR, Ndi\Params\MaxInterrupt, Min, 0, "1000"
    HKR, Ndi\Params\MaxInterrupt, Max, 0, "30000"
    HKR, Ndi\Params\MaxInterrupt, Step, 0, "500"
    HKR, Ndi\Params\MaxInterrupt, Default, 0, "5000"
    
    HKR, Ndi\Params\*SpeedDuplex, ParamDesc, 0, %SpeedDuplex%
    HKR, Ndi\Params\*SpeedDuplex, Type, 0, "enum"
    HKR, Ndi\Params\*SpeedDuplex, Default, 0, "0"
    HKR, Ndi\Params\*SpeedDuplex\enum, "0", 0, %Auto%
    HKR, Ndi\Params\*SpeedDuplex\enum, "1", 0, %10MHD%
    HKR, Ndi\Params\*SpeedDuplex\enum, "2", 0, %10MFD%
    HKR, Ndi\Params\*SpeedDuplex\enum, "3", 0, %100MHD%
    HKR, Ndi\Params\*SpeedDuplex\enum, "4", 0, %100MFD%
    
    HKR, Ndi\Params\*ReceiveBuffers, ParamDesc, 0, %ReceiveBuffers%
    HKR, Ndi\Params\*ReceiveBuffers, Type, 0, "int"
    HKR, Ndi\Params\*ReceiveBuffers, Base, 0, "10"
    HKR, Ndi\Params\*ReceiveBuffers, Min, 0, "16"
    HKR, Ndi\Params\*ReceiveBuffers, Max, 0, "2048"
    HKR, Ndi\Params\*ReceiveBuffers, Step, 0, "16"
    HKR, Ndi\Params\*ReceiveBuffers, Default, 0, "512"
    
    HKR, Ndi\Params\*TransmitBuffers, ParamDesc, 0, %TransmitBuffers%
    HKR, Ndi\Params\*TransmitBuffers, Type, 0, "int"
    HKR, Ndi\Params\*TransmitBuffers, Base, 0, "10"
    HKR, Ndi\Params\*TransmitBuffers, Min, 0, "16"
    HKR, Ndi\Params\*TransmitBuffers, Max, 0, "1024"
    HKR, Ndi\Params\*TransmitBuffers, Step, 0, "16"
    HKR, Ndi\Params\*TransmitBuffers, Default, 0, "256"
    
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4, ParamDesc, 0, %TCPChksumOffv4%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4, Type, 0, "enum"
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4, Default, 0, "3"
    
    HKR, Ndi\Params\*IPChecksumOffloadIPv4, ParamDesc, 0, %IPChksumOffv4%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4, Type, 0, "enum"
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4, Default, 0, "3"
    
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4, ParamDesc, 0, %UDPChksumOffv4%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4, Type, 0, "enum"
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4, Default, 0, "3"
    
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, ParamDesc, 0, %TCPChksumOffv6%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, Type, 0, "enum"
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, Default, 0, "3"
    
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, ParamDesc, 0, %UDPChksumOffv6%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, Type, 0, "enum"
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, Default, 0, "3"
    
    HKR, Ndi\Params\*LsoV1IPv4, ParamDesc, 0, %LSOv1IPv4%
    HKR, Ndi\Params\*LsoV1IPv4, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV1IPv4\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV1IPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV1IPv4, Default, 0, "1"
     
  13. limeay

    limeay Active Member

    Messages:
    60
    Likes Received:
    1
    GPU:
    Nvidia GTX 1080 Ti
    Code:
    HKR, Ndi\Params\*LsoV2IPv4, ParamDesc, 0, %LSOv2IPv4%
    HKR, Ndi\Params\*LsoV2IPv4, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV2IPv4\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV2IPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV2IPv4, Default, 0, "0"
    
    HKR, Ndi\Params\*LsoV2IPv6, ParamDesc, 0, %LSOv2IPv6%
    HKR, Ndi\Params\*LsoV2IPv6, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV2IPv6\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV2IPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV2IPv6, Default, 0, "0"
    
    HKR, Ndi\Params\NetworkAddress, ParamDesc, 0, %NetAddress%
    HKR, Ndi\Params\NetworkAddress, Type, 0, "edit"
    HKR, Ndi\Params\NetworkAddress, LimitText, 0, "12"
    HKR, Ndi\Params\NetworkAddress, UpperCase, 0, "1"
    HKR, Ndi\Params\NetworkAddress, Default, 0, ""
    HKR, Ndi\Params\NetworkAddress, Optional, 0, "1"
    
    HKR, Ndi\Params\*InterruptModeration, ParamDesc, 0, %IntMod%
    HKR, Ndi\Params\*InterruptModeration, Type, 0, "enum"
    HKR, Ndi\Params\*InterruptModeration\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*InterruptModeration\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*InterruptModeration, Default, 0, "1"
    
    HKR, Ndi\Params\*FlowControl, ParamDesc, 0, %FlowCtrl%
    HKR, Ndi\Params\*FlowControl, Type, 0, "enum"
    HKR, Ndi\Params\*FlowControl\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*FlowControl\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*FlowControl, Default, 0, "0"
    
    HKR, Ndi\Params\VLanID, ParamDesc, 0, %VLanID%
    HKR, Ndi\Params\VLanID, Type, 0, "long"
    HKR, Ndi\Params\VLanID, Base, 0, "10"
    HKR, Ndi\Params\VLanID, Min, 0, "0"
    HKR, Ndi\Params\VLanID, Max, 0, "4094"
    HKR, Ndi\Params\VLanID, Step, 0, "1"
    HKR, Ndi\Params\VLanID, Default, 0, "0"
    
    HKR, Ndi\Params\Ioac_SwoiSupported, ParamDesc, 0, %SWOI%
    HKR, Ndi\Params\Ioac_SwoiSupported, Type, 0, "enum"
    HKR, Ndi\Params\Ioac_SwoiSupported\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\Ioac_SwoiSupported\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\Ioac_SwoiSupported, Default, 0, "0"
    
    [ECS.params]
    HKR, Ndi\Params\MaxInterrupt, ParamDesc, 0, %MaxIrq%
    HKR, Ndi\Params\MaxInterrupt, Type, 0, "int"
    HKR, Ndi\Params\MaxInterrupt, Base, 0, "10"
    HKR, Ndi\Params\MaxInterrupt, Min, 0, "1000"
    HKR, Ndi\Params\MaxInterrupt, Max, 0, "30000"
    HKR, Ndi\Params\MaxInterrupt, Step, 0, "500"
    HKR, Ndi\Params\MaxInterrupt, Default, 0, "5000"
    
    HKR, Ndi\Params\*SpeedDuplex, ParamDesc, 0, %SpeedDuplex%
    HKR, Ndi\Params\*SpeedDuplex, Type, 0, "enum"
    HKR, Ndi\Params\*SpeedDuplex, Default, 0, "0"
    HKR, Ndi\Params\*SpeedDuplex\enum, "0", 0, %Auto%
    HKR, Ndi\Params\*SpeedDuplex\enum, "1", 0, %10MHD%
    HKR, Ndi\Params\*SpeedDuplex\enum, "2", 0, %10MFD%
    HKR, Ndi\Params\*SpeedDuplex\enum, "3", 0, %100MHD%
    HKR, Ndi\Params\*SpeedDuplex\enum, "4", 0, %100MFD%
    HKR, Ndi\Params\*SpeedDuplex\enum, "6", 0, %1GFD%
    
    HKR, Ndi\Params\*ReceiveBuffers, ParamDesc, 0, %ReceiveBuffers%
    HKR, Ndi\Params\*ReceiveBuffers, Type, 0, "int"
    HKR, Ndi\Params\*ReceiveBuffers, Base, 0, "10"
    HKR, Ndi\Params\*ReceiveBuffers, Min, 0, "16"
    HKR, Ndi\Params\*ReceiveBuffers, Max, 0, "2048"
    HKR, Ndi\Params\*ReceiveBuffers, Step, 0, "16"
    HKR, Ndi\Params\*ReceiveBuffers, Default, 0, "512"
    
    HKR, Ndi\Params\*TransmitBuffers, ParamDesc, 0, %TransmitBuffers%
    HKR, Ndi\Params\*TransmitBuffers, Type, 0, "int"
    HKR, Ndi\Params\*TransmitBuffers, Base, 0, "10"
    HKR, Ndi\Params\*TransmitBuffers, Min, 0, "16"
    HKR, Ndi\Params\*TransmitBuffers, Max, 0, "1024"
    HKR, Ndi\Params\*TransmitBuffers, Step, 0, "16"
    HKR, Ndi\Params\*TransmitBuffers, Default, 0, "256"
    
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4, ParamDesc, 0, %TCPChksumOffv4%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4, Type, 0, "enum"
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv4, Default, 0, "3"
    
    HKR, Ndi\Params\*IPChecksumOffloadIPv4, ParamDesc, 0, %IPChksumOffv4%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4, Type, 0, "enum"
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*IPChecksumOffloadIPv4, Default, 0, "3"
    
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4, ParamDesc, 0, %UDPChksumOffv4%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4, Type, 0, "enum"
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv4, Default, 0, "3"
    
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, ParamDesc, 0, %TCPChksumOffv6%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, Type, 0, "enum"
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*TCPChecksumOffloadIPv6, Default, 0, "3"
    
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, ParamDesc, 0, %UDPChksumOffv6%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, Type, 0, "enum"
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "2", 0, %RXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "1", 0, %TXEna%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*UDPChecksumOffloadIPv6, Default, 0, "3"
    
    HKR, Ndi\Params\*LsoV1IPv4, ParamDesc, 0, %LSOv1IPv4%
    HKR, Ndi\Params\*LsoV1IPv4, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV1IPv4\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV1IPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV1IPv4, Default, 0, "1"
    
    HKR, Ndi\Params\*LsoV2IPv4, ParamDesc, 0, %LSOv2IPv4%
    HKR, Ndi\Params\*LsoV2IPv4, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV2IPv4\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV2IPv4\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV2IPv4, Default, 0, "0"
    
    HKR, Ndi\Params\*LsoV2IPv6, ParamDesc, 0, %LSOv2IPv6%
    HKR, Ndi\Params\*LsoV2IPv6, Type, 0, "enum"
    HKR, Ndi\Params\*LsoV2IPv6\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*LsoV2IPv6\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*LsoV2IPv6, Default, 0, "0"
    
    HKR, Ndi\Params\NetworkAddress, ParamDesc, 0, %NetAddress%
    HKR, Ndi\Params\NetworkAddress, Type, 0, "edit"
    HKR, Ndi\Params\NetworkAddress, LimitText, 0, "12"
    HKR, Ndi\Params\NetworkAddress, UpperCase, 0, "1"
    HKR, Ndi\Params\NetworkAddress, Default, 0, ""
    HKR, Ndi\Params\NetworkAddress, Optional, 0, "1"
    
    HKR, Ndi\Params\*InterruptModeration, ParamDesc, 0, %IntMod%
    HKR, Ndi\Params\*InterruptModeration, Type, 0, "enum"
    HKR, Ndi\Params\*InterruptModeration\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*InterruptModeration\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*InterruptModeration, Default, 0, "1"
    
    HKR, Ndi\Params\*FlowControl, ParamDesc, 0, %FlowCtrl%
    HKR, Ndi\Params\*FlowControl, Type, 0, "enum"
    HKR, Ndi\Params\*FlowControl\enum, "3", 0, %TXRXEna%
    HKR, Ndi\Params\*FlowControl\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*FlowControl, Default, 0, "0"
    
    HKR, Ndi\Params\VLanID, ParamDesc, 0, %VLanID%
    HKR, Ndi\Params\VLanID, Type, 0, "long"
    HKR, Ndi\Params\VLanID, Base, 0, "10"
    HKR, Ndi\Params\VLanID, Min, 0, "0"
    HKR, Ndi\Params\VLanID, Max, 0, "4094"
    HKR, Ndi\Params\VLanID, Step, 0, "1"
    HKR, Ndi\Params\VLanID, Default, 0, "0"
    
    HKR, Ndi\Params\Ioac_SwoiSupported, ParamDesc, 0, %SWOI%
    HKR, Ndi\Params\Ioac_SwoiSupported, Type, 0, "enum"
    HKR, Ndi\Params\Ioac_SwoiSupported\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\Ioac_SwoiSupported\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\Ioac_SwoiSupported, Default, 0, "0"
    
    [WOLDefault.params]
    HKR, Ndi\Params\*WakeOnMagicPacket, ParamDesc, 0, %MagicPacket%
    HKR, Ndi\Params\*WakeOnMagicPacket, Type, 0, "enum"
    HKR, Ndi\Params\*WakeOnMagicPacket\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*WakeOnMagicPacket\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*WakeOnMagicPacket, Default, 0, "1"
    
    HKR, Ndi\Params\*WakeOnPattern, ParamDesc, 0, %PatternMatch%
    HKR, Ndi\Params\*WakeOnPattern, Type, 0, "enum"
    HKR, Ndi\Params\*WakeOnPattern\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*WakeOnPattern\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*WakeOnPattern, Default, 0, "1"
    
    [WOLMagic.params]
    HKR, Ndi\Params\*WakeOnMagicPacket, ParamDesc, 0, %MagicPacket%
    HKR, Ndi\Params\*WakeOnMagicPacket, Type, 0, "enum"
    HKR, Ndi\Params\*WakeOnMagicPacket\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*WakeOnMagicPacket\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*WakeOnMagicPacket, Default, 0, "1"
    
    HKR, Ndi\Params\*WakeOnPattern, ParamDesc, 0, %PatternMatch%
    HKR, Ndi\Params\*WakeOnPattern, Type, 0, "enum"
    HKR, Ndi\Params\*WakeOnPattern\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*WakeOnPattern\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*WakeOnPattern, Default, 0, "0"
    
    [WOLNone.params]
    HKR, Ndi\Params\*WakeOnMagicPacket, ParamDesc, 0, %MagicPacket%
    HKR, Ndi\Params\*WakeOnMagicPacket, Type, 0, "enum"
    HKR, Ndi\Params\*WakeOnMagicPacket\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*WakeOnMagicPacket\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*WakeOnMagicPacket, Default, 0, "0"
    
    HKR, Ndi\Params\*WakeOnPattern, ParamDesc, 0, %PatternMatch%
    HKR, Ndi\Params\*WakeOnPattern, Type, 0, "enum"
    HKR, Ndi\Params\*WakeOnPattern\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*WakeOnPattern\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*WakeOnPattern, Default, 0, "0"
    
    [PM.params]
    HKR, Ndi\Params\*PMARPOffload, ParamDesc, 0, %ARPOffload%
    HKR, Ndi\Params\*PMARPOffload, Type, 0, "enum"
    HKR, Ndi\Params\*PMARPOffload\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*PMARPOffload\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*PMARPOffload, Default, 0, "1"
    
    HKR, Ndi\Params\*PMNSOffload, ParamDesc, 0, %NSOffload%
    HKR, Ndi\Params\*PMNSOffload, Type, 0, "enum"
    HKR, Ndi\Params\*PMNSOffload\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*PMNSOffload\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*PMNSOffload, Default, 0, "1"
    
    [ShutOn.params]
    HKR, Ndi\Params\ShutdownWake, ParamDesc, 0, %ShutDW%
    HKR, Ndi\Params\ShutdownWake, Type, 0, "enum"
    HKR, Ndi\Params\ShutdownWake\enum, 1, 0, %Enabled%
    HKR, Ndi\Params\ShutdownWake\enum, 0, 0, %Disabled%
    HKR, Ndi\Params\ShutdownWake, Default, 0, "1"
    
    [ShutOff.params]
    HKR, Ndi\Params\ShutdownWake, ParamDesc, 0, %ShutDW%
    HKR, Ndi\Params\ShutdownWake, Type, 0, "enum"
    HKR, Ndi\Params\ShutdownWake\enum, 1, 0, %Enabled%
    HKR, Ndi\Params\ShutdownWake\enum, 0, 0, %Disabled%
    HKR, Ndi\Params\ShutdownWake, Default, 0, "0"
    
    [EEELPI.params]
    HKR, Ndi\Params\*EEE, ParamDesc, 0, %EEE%
    HKR, Ndi\Params\*EEE, Type, 0, "enum"
    HKR, Ndi\Params\*EEE\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*EEE\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*EEE, Default, 0, "1"
    
    [EEELPIEn.params]
    HKR, Ndi\Params\*EEE, ParamDesc, 0, %EEE%
    HKR, Ndi\Params\*EEE, Type, 0, "enum"
    HKR, Ndi\Params\*EEE\enum, "1", 0, %Enabled%
    HKR, Ndi\Params\*EEE\enum, "0", 0, %Disabled%
    HKR, Ndi\Params\*EEE, Default, 0, "1"
    ;-----------------------------------------------------------------------------
    ; DestinationDirs
    ;
    [L1C.CopyFiles]
    e2xw10x64.sys,,,2
    
    [SourceDisksNames]
    ;
    ; diskid = description[, [tagfile] [, <unused>, subdir]]
    ;
    1 = %DiskDescription%,,,
    
    [SourceDisksFiles]
    ;
    ; filename_on_source = diskID[, [subdir][, size]]
    ;
    e2xw10x64.sys = 1
    
    [DestinationDirs]
    L1C.CopyFiles = 12
    DefaultDestDir = 11
    
    [Strings]
    RIVET = "Rivet Networks"
    JumboFrame = "Jumbo Frame"
    2KBMTU = "2KB MTU"
    3KBMTU = "3KB MTU"
    4KBMTU = "4KB MTU"
    5KBMTU = "5KB MTU"
    6KBMTU = "6KB MTU"
    7KBMTU = "7KB MTU"
    8KBMTU = "8KB MTU"
    9KBMTU = "9KB MTU"
    IntMod = "Interrupt Moderation"
    L0sL1Threshold = "L0sL1 Gateway"
    MaxIrq = "Max IRQ per Second"
    Enabled = "Enabled"
    Disabled = "Disabled"
    SpeedDuplex = "Speed & Duplex"
    Auto = "Auto Negotiation"
    1GFD = "1.0 Gbps Full Duplex"
    10MHD = "10 Mbps Half Duplex"
    10MFD = "10 Mbps Full Duplex"
    100MHD = "100 Mbps Half Duplex"
    100MFD = "100 Mbps Full Duplex"
    FlowCtrl = "Flow Control"
    ShutDW = "Shutdown Wake Up"
    RSS = "Receive Side Scaling"
    TXEna = "Tx Enabled"
    RXEna = "Rx Enabled"
    TXRXEna = "Rx & Tx Enabled"
    ReceiveBuffers = "Receive Buffers"
    TransmitBuffers = "Transmit Buffers"
    IPChksumOffv4 = "IPv4 Checksum Offload"
    TCPChksumOffv4 = "TCP Checksum Offload (IPv4)"
    TCPChksumOffv6 = "TCP Checksum Offload (IPv6)"
    UDPChksumOffv4 = "UDP Checksum Offload (IPv4)"
    UDPChksumOffv6 = "UDP Checksum Offload (IPv6)"
    LSOv1IPv4 = "Large Send Offload (IPv4)"
    LSOv2IPv4 = "Large Send Offload v2 (IPv4)"
    LSOv2IPv6 = "Large Send Offload v2 (IPv6)"
    NetAddress = "Network Address"
    WakeUpCapabilities = "Wake Up Capabilities"
    APSmode = "APS mode"
    AZPower = "802.3az"
    None = "None"
    LinkChange = "Link Change"
    MagicPacket = "Wake on magic packet"
    PatternMatch = "Wake on pattern match"
    MagicPacket_PatternMatch = "MagicPacket & PatternMatch"
    VLanID = "VLAN ID"
    All = "All"
    EEE = "Energy Efficient Ethernet"
    ARPOffload = "ARP Offload"
    NSOffload = "NS Offload"
    ECMA = "ECMA"
    RssQs = "Maximum Number of RSS Queues"
    SWOI = "SWOI"
    RIVET.Service.DispName = "NDIS Miniport Driver for Killer PCI-E Gigabit Ethernet Controller"
    DiskDescription = "Killer Series PCI-E Gigabit Ethernet Controller Installation Disk"
    RIVET.L1F.E22 = "Killer E2200 Gigabit Ethernet Controller"
    RIVET.L1F.E24 = "Killer E2400 Gigabit Ethernet Controller"
    RIVET.L1F.E25 = "Killer E2500 Gigabit Ethernet Controller"
     
  14. limeay

    limeay Active Member

    Messages:
    60
    Likes Received:
    1
    GPU:
    Nvidia GTX 1080 Ti
    Qualcomm Atheros AR8161 V2.1.0.27 SO MUCH FRIGGIN CODE. 20k characters not enough lol

    Code:
    ;*****************************************************************************
    ;*
    ;*  L1C63x64.INF  -   Qualcomm Atheros AR813X/AR815X/AR816X Series PCI-E Ethernet Controller
    ;*  Copyright 2012-, Qualcomm Atheros Co., Ltd.
    ;*
    ;*  Created on 02/13/2012 by Yu Hao
    ;*  INF File for NDIS6.3 Miniport Driver for Windows8 x64
    ;*
    ;*****************************************************************************
    [Version]
    Signature   = "$Windows NT$"
    Class       = Net
    ClassGUID   = {4d36e972-e325-11ce-bfc1-08002be10318}
    Provider    = %ATHR%
    CatalogFile = netl1cx64.cat
    DriverVer=09/18/2017,2.1.0.27
    
    [Manufacturer]
    %ATHR% = Atheros, NTamd64
    
    [ControlFlags]
    ExcludeFromSelect    = *
    
    [Atheros.NTamd64]
    ; DisplayName           Section                DeviceID
    ; -----------           -------                   --------
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063                                ; L1C
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_10631969&REV_C0
    
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_83041043&REV_C0         ; ASUS
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_83FE1043&REV_C0         ; ASUS
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_84921043&REV_C0         ; ASUS
    %ATHR.L1C%   =          L1C.DisS5.ndi,         PCI\VEN_1969&DEV_1063&SUBSYS_18201043&REV_C0         ; ASUS
    %ATHR.L1C%   =          L1C.DisS5.ndi,         PCI\VEN_1969&DEV_1063&SUBSYS_18301043&REV_C0         ; ASUS
    
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_10631849&REV_C0         ; Asrock
    
    %ATHR.L1C%   =          L1C.ShutOn.ndi,        PCI\VEN_1969&DEV_1063&SUBSYS_20081854&REV_C0         ; Pegatron
    %ATHR.L1C%   =          L1C.ShutOn.ndi,        PCI\VEN_1969&DEV_1063&SUBSYS_20091854&REV_C0         ; Pegatron
    %ATHR.L1C%   =          L1C.ShutOn.ndi,        PCI\VEN_1969&DEV_1063&SUBSYS_FF101854&REV_C0         ; Pegatron
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_202F1B0A&REV_C0         ; Pegatron
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_00C31B0A&REV_C0         ; Pegatron
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_00C91B0A&REV_C0         ; Pegatron
    
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_10D217C0&REV_C0         ; M10B1
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_10D717C0&REV_C0         ; Dagger
    
    %ATHR.L1C%   =          L1C.Lenovo.ndi,        PCI\VEN_1969&DEV_1063&SUBSYS_394E17AA&REV_C0         ; NAUR2,NAWA
    %ATHR.L1C%   =          L1C.Lenovo.ndi,        PCI\VEN_1969&DEV_1063&SUBSYS_395817AA&REV_C0         ; NIMUA/B
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_395617AA&REV_C0         ; LU16_INTEL
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_396117AA&REV_C0         ; LU16_AMD
    
    %ATHR.L1C%   =          L1C.GIGABYTE.ndi,      PCI\VEN_1969&DEV_1063&SUBSYS_E0001458&REV_C0         ; GIGABYTE
    
    %ATHR.L1C%   =          L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_81311019&REV_C0         ; ECS
    
    %ATHR.L1C%   =           L1C.Toshiba.ndi,       PCI\VEN_1969&DEV_1063&SUBSYS_FF501179&REV_C0         ; TZ2
                                                                                             
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_02291025&REV_C0         ; JM31
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_027F1025&REV_C0         ; JM31
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_02801025&REV_C0         ; JM31
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_02381025&REV_C0         ; SJM31
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_02811025&REV_C0         ; SJM31
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_02821025&REV_C0         ; SJM31
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_03021025&REV_C0         ; SJM52
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_03031025&REV_C0         ; SJM52
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_03041025&REV_C0         ; SJM52
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_022A1025&REV_C0         ; JM41
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_022B1025&REV_C0         ; JM51
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_034B1025&REV_C0         ; NCL20
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_04301025&REV_C0         ; SJM40
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_04311025&REV_C0         ; SJM40
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_04321025&REV_C0         ; SJM40
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_04331025&REV_C0         ; SJM40
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_04341025&REV_C0         ; SJM40
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_04111025&REV_C0         ; NCWH1
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_041C1025&REV_C0         ; SJM30
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_041D1025&REV_C0         ; SJM30
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_042B1025&REV_C0         ; SJM50
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_042C1025&REV_C0         ; SJM30
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_04201025&REV_C0         ; SJM50NP_UMA
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_04211025&REV_C0         ; SJM50NP_UMA
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_041E1025&REV_C0         ; SJM50CP_UMA
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_041F1025&REV_C0         ; SJM50CP_DIS
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_04501025&REV_C0         ; SJM40
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_044F1025&REV_C0         ; SJM40
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_049B1025&REV_C0         ; HM55_MV
                                                                                             
    %ATHR.L1C%   =           L1C.SONY.ndi,          PCI\VEN_1969&DEV_1063&SUBSYS_390217AA&REV_C0         ; LU15
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_395617AA&REV_C0         ; LA46
                                                                                             
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_01671025&REV_C0         ; KAL90
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_021B1025&REV_C0         ; KBLG0
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_02601025&REV_C0         ; KALG0
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_027D1025&REV_C0         ; NBLG0
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_01281025&REV_C0         ; KALH0
                                                                                             
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_004214C0&REV_C0         ; NBLB1
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_004314C0&REV_C0         ; NBLB2
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_004514C0&REV_C0         ; NTTB1
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_004614C0&REV_C0         ; NTUC0
                                                                                             
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_021E1025&REV_C0         ; ZK6
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_02531025&REV_C0         ; ZR6
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_026A1025&REV_C0         ; ZK8
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_026D1025&REV_C0         ; ZK8
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_026E1025&REV_C0         ; ZK8
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_029B1025&REV_C0         ; ZH7
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_029F1025&REV_C0         ; ZH8
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_029E1025&REV_C0         ; ZH6
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_03001025&REV_C0         ; ZE8
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_029D1025&REV_C0         ; ZE9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_03321025&REV_C0         ; ZH9
                                                                                             
    %ATHR.L1C%   =           L1C.ShutOn.ndi,        PCI\VEN_1969&DEV_1063&SUBSYS_7009103C&REV_C0         ; SP7
    %ATHR.L1C%   =           L1C.ShutOn.ndi,        PCI\VEN_1969&DEV_1063&SUBSYS_1522103C&REV_C0         ; Nikita
    %ATHR.L1C%   =           L1C.ShutOn.ndi,        PCI\VEN_1969&DEV_1063&SUBSYS_147D103C&REV_C0         ; Nikita1.2
     
    Last edited: Dec 18, 2018
  15. limeay

    limeay Active Member

    Messages:
    60
    Likes Received:
    1
    GPU:
    Nvidia GTX 1080 Ti
    Code:
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_1411103C&REV_C0         ; ZENO
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_1412103C&REV_C0         ; ZENO
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_1413103C&REV_C0         ; ZENO
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_142C103C&REV_C0         ; PETEK
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_142D103C&REV_C0         ; PETEK
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_1421103C&REV_C0         ; Hamilton
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_1423103C&REV_C0         ; Hamilton
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_1420103C&REV_C0         ; Prano
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_142B103C&REV_C0         ; Prano
                                                                                              
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0D4E105B&REV_C0         ; AJ-BOX
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0D52105B&REV_C0         ; AJ-BOX-N
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0CD9105B&REV_C0         ; Clone
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0D56105B&REV_C0         ; Clone
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0CDA105B&REV_C0         ; Clone
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0E35105B&REV_C0         ; Clone
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0D57105B&REV_C0         ; Clone
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0CFC105B&REV_C0         ; Clone
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0CFD105B&REV_C0         ; Clone
    %ATHR.L1C%   =           L1C.ShutOn.ndi,        PCI\VEN_1969&DEV_1063&SUBSYS_0DC5105B&REV_C0         ; Clone
                                                                                              
    %ATHR.L1C%   =           L1C.WOLMagic.ndi,      PCI\VEN_1969&DEV_1063&SUBSYS_07991854&REV_C0         ; QL2
    %ATHR.L1C%   =           L1C.WOLMagic.ndi,      PCI\VEN_1969&DEV_1063&SUBSYS_08001854&REV_C0         ; QL2
    %ATHR.L1C%   =           L1C.WOLMagic.ndi,      PCI\VEN_1969&DEV_1063&SUBSYS_08031854&REV_C0         ; QL4
    %ATHR.L1C%   =           L1C.WOLMagic.ndi,      PCI\VEN_1969&DEV_1063&SUBSYS_08041854&REV_C0         ; QL4
    %ATHR.L1C%   =           L1C.WOLMagic.ndi,      PCI\VEN_1969&DEV_1063&SUBSYS_08051854&REV_C0         ; QL2
    %ATHR.L1C%   =           L1C.WOLMagic.ndi,      PCI\VEN_1969&DEV_1063&SUBSYS_08071854&REV_C0         ; QL4
    %ATHR.L1C%   =           L1C.WOLMagic.ndi,      PCI\VEN_1969&DEV_1063&SUBSYS_08211854&REV_C0         ; QL4
    %ATHR.L1C%   =           L1C.WOLMagic.ndi,      PCI\VEN_1969&DEV_1063&SUBSYS_08321854&REV_C0         ; QL4
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_20101854&REV_C0         ; PEGATRON
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_20111854&REV_C0         ; PEGATRON
                                                                                              
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0809152D&REV_C0         ; SW9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0810152D&REV_C0         ; SW9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0812152D&REV_C0         ; TW9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0813152D&REV_C0         ; TW9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0814152D&REV_C0         ; SW9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0815152D&REV_C0         ; TW9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0822152D&REV_C0         ; TW9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0828152D&REV_C0         ; TW9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0831152D&REV_C0         ; TW9A
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0835152D&REV_C0         ; SW9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0852152D&REV_C0         ; TW9D
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0853152D&REV_C0         ; TW9D
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0854152D&REV_C0         ; TW9E
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0855152D&REV_C0         ; SW9
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_0856152D&REV_C0         ; SW9D
                                                                                              
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_041E1028&REV_C0         ; Dell-DC1
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_041F1028&REV_C0         ; Dell-DC2
                                                                                              
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_906A104D&REV_C0         ; NEO
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_9069104D&REV_C0         ; NEO
    %ATHR.L1C%   =           L1C.SONY.ndi,          PCI\VEN_1969&DEV_1063&SUBSYS_906F104D&REV_C0         ; Sony
    %ATHR.L1C%   =           L1C.SONY.ndi,          PCI\VEN_1969&DEV_1063&SUBSYS_9076104D&REV_C0         ; Cadiz
    %ATHR.L1C%   =           L1C.WOLMagic.ndi,      PCI\VEN_1969&DEV_1063&SUBSYS_906C104D&REV_C0         ; TW6
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_907C104D&REV_C0         ; Tucana
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_9082104D&REV_C0         ; Tucana-BR
                                                                                              
    %ATHR.L1C%   =           L1C.ndi,               PCI\VEN_1969&DEV_1063&SUBSYS_10D217C0&REV_C0         ; M10B1
                                                                                              
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062                                ; L2C
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_10621969&REV_C0         ;
                                                                                              
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_83041043&REV_C0         ; ASUS
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_83FF1043&REV_C0         ; ASUS
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_838A1043&REV_C0         ; EEEPC
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_83BE1043&REV_C0         ; EEEPC
    %ATHR.L2C%   =          L2C.DisS5.ndi,         PCI\VEN_1969&DEV_1062&SUBSYS_14E51043&REV_C0         ; F50Q
    %ATHR.L2C%   =          L2C.DisS5.ndi,         PCI\VEN_1969&DEV_1062&SUBSYS_15251043&REV_C0         ; ASUS
    
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_10621849&REV_C0         ; Asrock
                                                                                              
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_81321019&REV_C0         ; ECS
                                                                                              
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_20261B0A&REV_C0         ; PEGATRON
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_1598103C&REV_C0         ; PEGATRON
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_2ACC103C&REV_C0         ; PEGATRON
    %ATHR.L2C%   =          L2C.WOLMagic.ndi,      PCI\VEN_1969&DEV_1062&SUBSYS_00AA1B0A&REV_C0         ; PEGATRON
    %ATHR.L2C%   =          L2C.ShutOn.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_20081854&REV_C0         ; PEGATRON
    %ATHR.L2C%   =          L2C.ShutOn.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_20091854&REV_C0         ; PEGATRON
    %ATHR.L2C%   =          L2C.ShutOn.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_200A1854&REV_C0         ; PEGATRON
    %ATHR.L2C%   =          L2C.ShutOn.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_200B1854&REV_C0         ; PEGATRON
    %ATHR.L2C%   =          L2C.ShutOn.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_200D1854&REV_C0         ; PEGATRON, H00J
    %ATHR.L2C%   =          L2C.ShutOn.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_200E1854&REV_C0         ; PEGATRON
    %ATHR.L2C%   =          L2C.ShutOn.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_00E01B0A&REV_C0         ; PEGATRON
                                                                                              
    %ATHR.L2C%   =          L2C.GIGABYTE.ndi,      PCI\VEN_1969&DEV_1062&SUBSYS_E0001458&REV_C0         ; GIGABYTE
                                                                                              
    %ATHR.L2C%   =          L2C.Lenovo.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_394F17AA&REV_C0         ; NAUR2,NAWA
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_38A317AA&REV_C0         ; LA14
    %ATHR.L2C%   =          L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_395617AA&REV_C0         ; LA46
    %ATHR.L2C%   =          L2C.Lenovo.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_395817AA&REV_C0         ; NIMUA/B
                                                                                              
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_019C1025&REV_C0         ; KAV10
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02101025&REV_C0         ; KAWH0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02111025&REV_C0         ; KBWH0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02121025&REV_C0         ; KAWF0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02131025&REV_C0         ; KAWG0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02141025&REV_C0         ; HM40-MV
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02151025&REV_C0         ; HM40-YK
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02161025&REV_C0         ; HM20-YK
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_019D1025&REV_C0         ;
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_022E1025&REV_C0         ; KAW10
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_022F1025&REV_C0         ; KAV50
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02301025&REV_C0         ; KAV60
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02411025&REV_C0         ; KAV80
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02431025&REV_C0         ; KAVA0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02601025&REV_C0         ; KALG0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_028D1025&REV_C0         ; HM50/70-PU
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_03491025&REV_C0         ; NAV50
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_034A1025&REV_C0         ; NAV60
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_030D1025&REV_C0         ; HM41
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_03501025&REV_C0         ; HM50/51/70
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04111025&REV_C0         ; NCWH1
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04391025&REV_C0         ; NAVD0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_043A1025&REV_C0         ; NAVD0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_043B1025&REV_C0         ; NAVE0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_043C1025&REV_C0         ; NAVE0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04591025&REV_C0         ; JE50_MV
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_045A1025&REV_C0         ; HM52_MV
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_045B1025&REV_C0         ; BA51_MV
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04971025&REV_C0         ; PAV50
                                                                                              
    %ATHR.L2C%   =           L2C.ShutOn.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_308F103C&REV_C0         ; BIXBY
    %ATHR.L2C%   =           L2C.ShutOn.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_1468103C&REV_C0         ; BIXBY 2.0
    %ATHR.L2C%   =           L2C.ShutOn.ndi,        PCI\VEN_1969&DEV_1062&SUBSYS_1492103C                ;
                                                                                              
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_0820152D&REV_C0         ; UW2
                                                                                              
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04091028&REV_C0         ; ARGOS
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04431028&REV_C0         ; Phantom
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04511028&REV_C0         ; DJ
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04521028&REV_C0         ; DJ
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04531028&REV_C0         ; DJ
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04541028&REV_C0         ; DJ
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04651028&REV_C0         ; NAP10
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04661028&REV_C0         ; DJx
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04701028&REV_C0         ; NLM01
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04711028&REV_C0         ; NLM00
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_046F1028&REV_C0         ; DJ1_AMD
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04A61028&REV_C0        ; DJ2_MV
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_049E1028&REV_C0        ; DJ2_AMD
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_049F1028&REV_C0        ; DJ2_CP_UMA
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_04A01028&REV_C0        ; DJ2_CP_DIS
                                                                                              
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_004414C0&REV_C0         ; NTTB0
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_004714C0&REV_C0         ; NTV00/10
                                                                                              
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_022C1025&REV_C0         ; ZG8
    %ATHR.L2C%   =           L2C.Toshiba.ndi,       PCI\VEN_1969&DEV_1062&SUBSYS_FF501179&REV_C0         ; TZ2
    %ATHR.L2C%   =           L2C.Toshiba.ndi,       PCI\VEN_1969&DEV_1062&SUBSYS_FFE01179&REV_C0         ; BU3
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_0790152D&REV_C0         ; IN1
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_02441025&REV_C0         ; ZA3
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_9064104D&REV_C0         ; SY2
    %ATHR.L2C%   =           L2C.ndi,               PCI\VEN_1969&DEV_1062&SUBSYS_9066104D&REV_C0         ; SY3
                                                                                              
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060                        ; L2cB       
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_20601969&REV_C1         ; L2cB
                                                                                                
    %ATHR.L2CB%  =           L2CB.PWMAll.ndi,       PCI\VEN_1969&DEV_2060&SUBSYS_FF1E1179&REV_C1         ; IEC
    %ATHR.L2CB%  =           L2CB.PWMAll.ndi,       PCI\VEN_1969&DEV_2060&SUBSYS_FDD01179&REV_C1         ; TE6
     

  16. limeay

    limeay Active Member

    Messages:
    60
    Likes Received:
    1
    GPU:
    Nvidia GTX 1080 Ti
    Code:
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_04511028&REV_C1         ; DJ1_MV                                                                                             
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_04551028&REV_C1         ; UM7
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_04561028&REV_C1         ; UM8
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_04571028&REV_C1         ; UM9
    %ATHR.L2CB%  =           L2CB.ASPM1.ndi,        PCI\VEN_1969&DEV_2060&SUBSYS_04661028&REV_C1         ; DJ1_CP
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_046F1028&REV_C1         ; DJ1_AMD
    %ATHR.L2CB%  =           L2CB.ASPM1.ndi,        PCI\VEN_1969&DEV_2060&SUBSYS_04861028&REV_C1         ; DJ2_CP
    %ATHR.L2CB%  =           L2CB.ASPM1.ndi,        PCI\VEN_1969&DEV_2060&SUBSYS_04871028&REV_C1         ; DJ2_AMD
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_048F1028&REV_C1         ; Dell_Avenger
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_04901028&REV_C1         ; Dell_Voyager
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_04A61028&REV_C1        ; DJ2_MV
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_049E1028&REV_C1         ; DJ2_AMD
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_049F1028&REV_C1         ; DJ2_CP_UMA
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_04A01028&REV_C1         ; DJ2_CP_DIS
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_04DF1028&REV_C1         ; Andros MLK
                                                                                                
    %ATHR.L2CB%  =           L2CB.ShutOn.ndi,       PCI\VEN_1969&DEV_2060&SUBSYS_147E103C&REV_C1         ; Bixby 3.0
                                                                                                
    %ATHR.L2CB%  =           L2CB.ShutOn.ndi,       PCI\VEN_1969&DEV_2060&SUBSYS_FD501179&REV_C1         ; TE2
    %ATHR.L2CB%  =           L2CB.ShutOn.ndi,       PCI\VEN_1969&DEV_2060&SUBSYS_FDD01179&REV_C1         ; BL6
                                                                                                
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_04291025&REV_C1         ; ZH9
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_043D1025&REV_C1         ; ZH9
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_043E1025&REV_C1         ; ZH9AB
    %ATHR.L2CB%  =           L2CB.ASPM1.ndi,        PCI\VEN_1969&DEV_2060&SUBSYS_03491025&REV_C1         ; NAV70
    %ATHR.L2CB%  =           L2CB.ASPM1.ndi,        PCI\VEN_1969&DEV_2060&SUBSYS_034A1025&REV_C1         ; NAV80
    %ATHR.L2CB%  =           L2CB.ASPM1.ndi,        PCI\VEN_1969&DEV_2060&SUBSYS_04971025&REV_C1         ; PAV50
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_048A1025&REV_C1         ; PEW72
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_05431025&REV_C1         ; P0VE6
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_05441025&REV_C1         ; P0VS6
                                                                                                
    %ATHR.L2CB%  =           L2CB.DisS5.ndi,        PCI\VEN_1969&DEV_2060&SUBSYS_396517AA&REV_C1         ; LL7
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_396B17AA&REV_C1         ; NAWEx
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_397917AA&REV_C1        ; PIWG1/2/3
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_397B17AA&REV_C1        ; PAWGx
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_398317AA&REV_C1        ; PAW10/20
                                                                                                
    %ATHR.L2CB%  =           L2CB.MB.ndi,           PCI\VEN_1969&DEV_2060&SUBSYS_81521019&REV_C1         ; ECS
    %ATHR.L2CB%  =           L2CB.MB.ndi,           PCI\VEN_1969&DEV_2060&SUBSYS_20601019&REV_C1         ; ECS
                                                                                                
    %ATHR.L2CB%  =           L2CB.FUJU.ndi,         PCI\VEN_1969&DEV_2060&SUBSYS_15DB10CF&REV_C1         ; UME
    
    %ATHR.L2CB%  =           L2CB.DisS5.ndi,        PCI\VEN_1969&DEV_2060&SUBSYS_18501043&REV_C1         ; ASUS
    %ATHR.L2CB%  =           L2CB.ndi,              PCI\VEN_1969&DEV_2060&SUBSYS_84681043&REV_C1         ; ASUS
    
    %ATHR.L2CB%  =           L2CB.MB.ndi,           PCI\VEN_1969&DEV_2060&SUBSYS_E0001458&REV_C1         ; GIGABYTE
                                                                                                
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073                        ; L1d           
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_10731969&REV_C0         ; L1d
                                                                                                
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_03561025&REV_C0         ; ZQ1
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_03571025&REV_C0         ; ZQ1
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_03581025&REV_C0         ; ZQ1B
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_03591025&REV_C0         ; ZQ1B
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_035A1025&REV_C0         ; ZR7
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_035B1025&REV_C0         ; ZR7
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_035C1025&REV_C0         ; ZR7B
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_035D1025&REV_C0         ; ZR7B
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_035E1025&REV_C0         ; ZQ2
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_03601025&REV_C0         ; ZR8
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_03621025&REV_C0         ; ZR8B
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_03661025&REV_C0         ; ZQ2B
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_03641025&REV_C0         ; JM31
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_03671025&REV_C0         ; ZYA
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_03681025&REV_C0         ; ZYA
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_038B1025&REV_C0         ; ZYB
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_038C1025&REV_C0         ; ZYB
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04121025&REV_C0         ; ZYD
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_040E1025&REV_C0         ; JV10
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04281025&REV_C0         ; SJV10
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04291025&REV_C0         ; JV10_NL
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_040D1025&REV_C0         ; SJV10_NL
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04601025&REV_C0         ; JV10_CP
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_045F1025&REV_C0         ; JV10_NL
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04631025&REV_C0         ; ZR7D
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04641025&REV_C0         ; JV53_CP
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04651025&REV_C0         ; JV53_CP
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04731025&REV_C0         ; SJM70_CP
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04751025&REV_C0         ; SJM70_CP
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04761025&REV_C0         ; SJM70_CP
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_047E1025&REV_C0         ; PAU30
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_048A1025&REV_C0         ; PEW72
    %ATHR.L1D%  =           L1D.TxPerf.ndi,           PCI\VEN_1969&DEV_1073&SUBSYS_050E1025&REV_C0         ; P7YE0
    %ATHR.L1D%  =           L1D.TxPerf.ndi,        PCI\VEN_1969&DEV_1073&SUBSYS_050F1025&REV_C0         ; P7YE0
    %ATHR.L1D%  =           L1D.TxPerf.ndi,        PCI\VEN_1969&DEV_1073&SUBSYS_05131025&REV_C0         ; P7YS0
    %ATHR.L1D%  =           L1D.TxPerf.ndi,        PCI\VEN_1969&DEV_1073&SUBSYS_05141025&REV_C0         ; P7YS0
    %ATHR.L1D%  =           L1D.TxPerf.ndi,        PCI\VEN_1969&DEV_1073&SUBSYS_05151025&REV_C0         ; P7YH0
    %ATHR.L1D%  =           L1D.TxPerf.ndi,        PCI\VEN_1969&DEV_1073&SUBSYS_05161025&REV_C0         ; P7YH0
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_054C1025&REV_C0         ; JM30
    %ATHR.L1D%  =           L1D.TxPerf.ndi,        PCI\VEN_1969&DEV_1073&SUBSYS_054E1025&REV_C0         ; JM30
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_05221025&REV_C0         ; JE73
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_05231025&REV_C0         ; JE73
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_05241025&REV_C0         ; SJ53
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_052A1025&REV_C0         ; SJ53
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_05571025&REV_C0         ; JE41
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_055F1025&REV_C0         ; JE51
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_054B1025&REV_C0         ; HM51
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_054D1025&REV_C0         ; HM51
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_054F1025&REV_C0         ; JM40
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_055B1025&REV_C0         ; JM50
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_05711025&REV_C0         ; SJM40
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_056D1025&REV_C0         ; BA70
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_056F1025&REV_C0         ; SJM50
     
  17. limeay

    limeay Active Member

    Messages:
    60
    Likes Received:
    1
    GPU:
    Nvidia GTX 1080 Ti
    Code:
    %ATHR.L1D%  =           L1D.ShutOn.ndi,        PCI\VEN_1969&DEV_1073&SUBSYS_FD501179&REV_C0         ; TE2
    %ATHR.L1D%  =           L1D.ShutOn.ndi,        PCI\VEN_1969&DEV_1073&SUBSYS_FDD01179&REV_C0         ; BL6
    %ATHR.L1D%  =           L1D.ToPatch.ndi,       PCI\VEN_1969&DEV_1073&SUBSYS_FF1E1179&REV_C0         ; Berlin
                                                                                                
    %ATHR.L1D%  =           L1D.DisS5.ndi,         PCI\VEN_1969&DEV_1073&SUBSYS_395B17AA&REV_C0         ; NAU00
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_396A17AA&REV_C0         ; NAWEx
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_395817AA&REV_C0         ; NIUM1
    %ATHR.L1D%  =           L1D.TxPerf.ndi,        PCI\VEN_1969&DEV_1073&SUBSYS_397917AA&REV_C0        ; PIWG1/2/3
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_397B17AA&REV_C0        ; PAWGx
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_398317AA&REV_C0        ; PAW10/20
                                                                                                
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_0CDD105B&REV_C0         ; W930
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_0D5E105B&REV_C0         ; Haier
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_0DBE105B&REV_C0         ; Clone
                                                                                                
    %ATHR.L1D%  =           L1D.MB.ndi,            PCI\VEN_1969&DEV_1073&SUBSYS_81511019&REV_C0         ; ECS
    %ATHR.L1D%  =           L1D.MB.ndi,            PCI\VEN_1969&DEV_1073&SUBSYS_10731019&REV_C0         ; ECS
    %ATHR.L1D%  =           L1D.ECSD.ndi,          PCI\VEN_1969&DEV_1073&SUBSYS_04731028&REV_C0         ; ECS/Dell
                                                                                                
    %ATHR.L1D%  =           L1D.DisS5.ndi,         PCI\VEN_1969&DEV_1073&SUBSYS_18041043&REV_C0         ; ASUS
    %ATHR.L1D%  =           L1D.DisS5.ndi,         PCI\VEN_1969&DEV_1073&SUBSYS_18401043&REV_C0         ; ASUS
    
    %ATHR.L1D%  =           L1D.MB.ndi,            PCI\VEN_1969&DEV_1073&SUBSYS_E0001458&REV_C0         ; GIGABYTE
    
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04511028&REV_C0         ; DJ1_MV
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04661028&REV_C0         ; DJ1_CP
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_046F1028&REV_C0         ; DJ1_AMD
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04861028&REV_C0         ; DJ2_CP
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04871028&REV_C0         ; DJ2_AMD
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_048F1028&REV_C0         ; Dell_Avenger
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04901028&REV_C0         ; Dell_Voyager
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04A61028&REV_C0         ; DJ2_MV
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_049E1028&REV_C0         ; DJ2_AMD
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_049F1028&REV_C0         ; DJ2_CP_UMA
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04A01028&REV_C0         ; DJ2_CP_DIS
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04911028&REV_C0         ; Spector
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_04C81028&REV_C0         ; Alienware
    
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_2AAE103C&REV_C0         ; Pegatron
    %ATHR.L1D%  =           L1D.ShutOn.ndi,        PCI\VEN_1969&DEV_1073&SUBSYS_207D1B0A&REV_C0         ; Pegatron
    
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08611854&REV_C0        ; QLH
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08621854&REV_C0        ; QLH
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08631854&REV_C0         ; QLH
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08641854&REV_C0         ; QLH
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08651854&REV_C0         ; QLH
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08661854&REV_C0         ; QLA
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08671854&REV_C0         ; QLA
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08681854&REV_C0         ; QLA
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08691854&REV_C0         ; QLC
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08701854&REV_C0         ; QLC
    %ATHR.L1D%  =           L1D.ndi,               PCI\VEN_1969&DEV_1073&SUBSYS_08711854&REV_C0         ; QLC
                                                                                                
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062                        ; L2cb 2.0     
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_20621969&REV_C0
                                                                                                
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_04861028&REV_C0         ; DJ2_CP
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_04871028&REV_C0         ; DJ2_AMD
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04511028&REV_C0         ; DJ1_MV
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04551028&REV_C0         ; UM7
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04561028&REV_C0         ; UM8
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04571028&REV_C0         ; UM9
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_04661028&REV_C0         ; DJ1_CP
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_046F1028&REV_C0         ; DJ1_AMD
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_048F1028&REV_C0         ; Dell_Avenger
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04901028&REV_C0         ; Dell_Voyager
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04A61028&REV_C0         ; DJ2_MV
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_049E1028&REV_C0         ; DJ2_AMD
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_049F1028&REV_C0         ; DJ2_CP_UMA
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04A01028&REV_C0         ; DJ2_CP_DIS
    
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FD501179&REV_C0         ; TE2
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FDD01179&REV_C0         ; BL6
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FF1E1179&REV_C0         ; IEC
                                                                                                
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_147E103C&REV_C0         ; Bixby 3.0                                                                                           
                                                                                                
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04291025&REV_C0         ; ZH9
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_043D1025&REV_C0         ; ZH9
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_043E1025&REV_C0         ; ZH9AB
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_03491025&REV_C0         ; NAV70
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_034A1025&REV_C0         ; NAV80
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_04971025&REV_C0         ; PAV50
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_048A1025&REV_C0         ; PEW72
                                                                                                
    %ATHR.L2CB%  =           L2CB2.DisS5.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_396517AA&REV_C0         ; LL7
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_396B17AA&REV_C0         ; NAWEx
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_397917AA&REV_C0        ; PIWG1/2/3
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_397B17AA&REV_C0        ; PAWGx
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_398317AA&REV_C0        ; PAW10/20
                                                                                                
    %ATHR.L2CB%  =           L2CB2.MB.ndi,          PCI\VEN_1969&DEV_2062&SUBSYS_81521019&REV_C0         ; ECS
    %ATHR.L2CB%  =           L2CB2.MB.ndi,          PCI\VEN_1969&DEV_2062&SUBSYS_20621019&REV_C0         ; ECS
                                                                                                
    %ATHR.L2CB%  =           L2CB2.FUJU.ndi,        PCI\VEN_1969&DEV_2062&SUBSYS_15DB10CF&REV_C0         ; UME
    
    %ATHR.L2CB%  =           L2CB2.DisS5.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_18501043&REV_C0         ; ASUS
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_84681043&REV_C0         ; ASUS
    
    %ATHR.L2CB%  =           L2CB2.MB.ndi,          PCI\VEN_1969&DEV_2062&SUBSYS_E0001458&REV_C0         ; GIGABYT
          
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_20621969&REV_C1        ; L2cb 2.1
                                                                                                
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_04861028&REV_C1         ; DJ2_CP
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_04871028&REV_C1         ; DJ2_AMD
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04511028&REV_C1         ; DJ1_MV
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04551028&REV_C1         ; UM7
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04561028&REV_C1         ; UM8
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04571028&REV_C1         ; UM9
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_04661028&REV_C1         ; DJ1_CP
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_046F1028&REV_C1         ; DJ1_AMD
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_048F1028&REV_C1         ; Dell_Avenger
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04901028&REV_C1         ; Dell_Voyager
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04A61028&REV_C1         ; DJ2_MV
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_049E1028&REV_C1         ; DJ2_AMD
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_049F1028&REV_C1         ; DJ2_CP_UMA
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04A01028&REV_C1         ; DJ2_CP_DIS
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04DF1028&REV_C1         ; Andros MLK
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04EA1028&REV_C1         ; Zuma
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_051B1028&REV_C1         ; Shakira
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_05501028&REV_C1         ; Avenger II
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_05511028&REV_C1         ; Voyager II
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_05521028&REV_C1         ; Spector II
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_057B1028&REV_C1         ; Voyager II
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_05801028&REV_C1         ; Voyager II
    
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FC761179&REV_C1         ; Ankara
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FC771179&REV_C1         ; Ankara
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FD7A1179&REV_C1         ; Ankara
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FD7B1179&REV_C1         ; Ankara
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FC671179&REV_C1         ; Celtic
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FD6A1179&REV_C1         ; Celtic
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FD6B1179&REV_C1         ; Celtic
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FD501179&REV_C1         ; TE2
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FDD01179&REV_C1         ; BL6
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FF1E1179&REV_C1         ; IEC
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FDD11179&REV_C1         ; TE7
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FFD61179&REV_C1         ; TZ6
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FCB31179&REV_C1         ; TE7
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FC501179&REV_C1         ; BLF
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FCD01179&REV_C1         ; TE5
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FCC01179&REV_C1         ; BU5
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FD521179&REV_C1         ; BLE
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FDD21179&REV_C1         ; BU4
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FD401179&REV_C1         ; BU4
    %ATHR.L2CB%  =           L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FC401179&REV_C1         ; BU6
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB901179&REV_C1         ; BU8
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB911179&REV_C1         ; BU8D
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB921179&REV_C1         ; BU8D
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FCD31179&REV_C1         ; BY5/BY5D
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB551179&REV_C1         ; BY6
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB561179&REV_C1         ; BY6D
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FCD21179&REV_C1         ; BY3
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FCD41179&REV_C1         ; BY3D
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FCD51179&REV_C1         ; BY3D
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FC551179&REV_C1         ; BY4
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FC561179&REV_C1         ; BY4D
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FC571179&REV_C1         ; BY4D
    %ATHR.L2CB%  =          L2CB2.FSWOL.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_FB501179&REV_C1         ; BY3C
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB511179&REV_C1         ; BY3G
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB521179&REV_C1         ; BY3G
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB801179&REV_C1         ; BY4C
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB811179&REV_C1         ; BY4G
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB821179&REV_C1         ; BY4G
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FCC51179&REV_C1         ; KZ1
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FC421179&REV_C1         ; BY1
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FBA01179&REV_C1         ; TEA
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FBA11179&REV_C1         ; BY2
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FBA21179&REV_C1         ; BY2D
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FAB31179&REV_C1         ; BY2D
    %ATHR.L2CB%  =          L2CB2.PWMAll.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_FB731179&REV_C1         ; BYD
                                                                                                
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_147E103C&REV_C1         ; Bixby 3.0
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_3584103C&REV_C1         ; Kitty
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_3585103C&REV_C1         ; Kitty   
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_3595103C&REV_C1         ; KID
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_2AE3103C&REV_C1         ; RedwoodA
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_2AE4103C&REV_C1         ; RedwoodB
     
  18. limeay

    limeay Active Member

    Messages:
    60
    Likes Received:
    1
    GPU:
    Nvidia GTX 1080 Ti
    Code:
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04291025&REV_C1         ; ZH9
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_043D1025&REV_C1         ; ZH9
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_043E1025&REV_C1         ; ZH9AB
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_03491025&REV_C1         ; NAV70
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_034A1025&REV_C1         ; NAV80
    %ATHR.L2CB%  =           L2CB2.ASPM1.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_04971025&REV_C1         ; PAV50
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_048A1025&REV_C1         ; PEW72
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_02291025&REV_C1         ; JM31
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_027F1025&REV_C1         ; JM31
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_02801025&REV_C1         ; JM31
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_03641025&REV_C1         ; JM31
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_040E1025&REV_C1         ; JV10
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04281025&REV_C1         ; SJV10
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04291025&REV_C1         ; JV10_NL
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_040D1025&REV_C1         ; SJV10_NL
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_04601025&REV_C1         ; SJV10_CP
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_045F1025&REV_C1         ; JV10_NL
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_05431025&REV_C1         ; P0VE6
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_05441025&REV_C1         ; P0VS6
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_05981025&REV_C1         ; P1VE6
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_06021025&REV_C1         ; HMA51-BZ
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_06031025&REV_C1         ; ZQJ
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_06041025&REV_C1         ; ZQQ
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_060A1025&REV_C1         ; SAZ70
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_060B1025&REV_C1         ; SIC70
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_060E1025&REV_C1         ; SAZ71
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_060F1025&REV_C1         ; SIC71
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_06101025&REV_C1         ; AIC70
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_06111025&REV_C1         ; AIC71
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_06141025&REV_C1         ; AAB70
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_06151025&REV_C1         ; AAB71
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_05041025&REV_C1         ;
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_061E1025&REV_C1         ; Q5WP1
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_06221025&REV_C1         ; HMA41
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_06231025&REV_C1         ; HMA51
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_063A1025&REV_C1          ; JE10-CT
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_07641025&REV_C1          ; V5VE1/T1
                                                                                                
    %ATHR.L2CB%  =           L2CB2.DisS5.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_396517AA&REV_C1         ; LL7
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_396B17AA&REV_C1         ; NAWEx
    %ATHR.L2CB%  =           L2CB2.TxPerf.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_397917AA&REV_C1        ; PIWG1/2/3
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_397B17AA&REV_C1        ; PAWGx
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_397717AA&REV_C1        ; Y490
                                                                                                
    %ATHR.L2CB%  =           L2CB2.MB.ndi,          PCI\VEN_1969&DEV_2062&SUBSYS_81521019&REV_C1         ; ECS
    %ATHR.L2CB%  =           L2CB2.MB.ndi,          PCI\VEN_1969&DEV_2062&SUBSYS_20621019&REV_C1         ; ECS
                                                                                                
    %ATHR.L2CB%  =           L2CB2.FUJU.ndi,        PCI\VEN_1969&DEV_2062&SUBSYS_15DB10CF&REV_C1         ; UME
    
    %ATHR.L2CB%  =           L2CB2.DisS5.ndi,       PCI\VEN_1969&DEV_2062&SUBSYS_18501043&REV_C1         ; ASUS
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_84681043&REV_C1         ; ASUS
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_100B1043&REV_C1         ; ASUS
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_103B1043&REV_C1          ; ASUS
    
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_20621849&REV_C1          ; Asrock
    
    %ATHR.L2CB%  =           L2CB2.MB.ndi,          PCI\VEN_1969&DEV_2062&SUBSYS_E0001458&REV_C1         ; GIGABYTE
    
    %ATHR.L2CB%  =           L2CB2.MB.ndi,          PCI\VEN_1969&DEV_2062&SUBSYS_28021565&REV_C1         ; BIOSTAR
    %ATHR.L2CB%  =           L2CB2.MB.ndi,          PCI\VEN_1969&DEV_2062&SUBSYS_28011565&REV_C1         ; BIOSTAR
    
    %ATHR.L2CB%  =           L2CB2.ndi,             PCI\VEN_1969&DEV_2062&SUBSYS_207E1B0A&REV_C1         ; Pegatron
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_2AAE103C&REV_C1         ; Pegatron
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_3580103C&REV_C1         ; Pegatron
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_2AD1103C&REV_C1         ; Pegatron
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_2AD3103C&REV_C1         ; Pegatron
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_2AD4103C&REV_C1         ; Pegatron
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_2AE2103C&REV_C1         ; Pegatron
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_2AF4103C&REV_C1         ; Pegatron
    
    %ATHR.L2CB%  =           L2CB2.ShutOn.ndi,      PCI\VEN_1969&DEV_2062&SUBSYS_0E2D105B&REV_C1         ; Livebox
    %ATHR.L2CB%  =           L2CB2.GIGABYTE.ndi,    PCI\VEN_1969&DEV_2062&SUBSYS_0D83105B&REV_C1         ; Foxconn
    %ATHR.L2CB%  =           L2CB2.SYS.ndi,         PCI\VEN_1969&DEV_2062&SUBSYS_2B01103C&REV_C1         ; Foxconn/Redwood2
    
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083                        ; L1d 2.0         
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_10831969&REV_C0         ;
    
    %ATHR.L1D%  =           L1D2.DisS5.ndi,        PCI\VEN_1969&DEV_1083&SUBSYS_18401043&REV_C0         ; ASUS
    %ATHR.L1D%  =           L1D2.DisS5.ndi,        PCI\VEN_1969&DEV_1083&SUBSYS_18511043&REV_C0         ; ASUS
    %ATHR.L1D%  =           L1D2.SYS.ndi,          PCI\VEN_1969&DEV_1083&SUBSYS_847E1043&REV_C0         ; ASUS
    %ATHR.L1D%  =           L1D2.SYS.ndi,          PCI\VEN_1969&DEV_1083&SUBSYS_84BF1043&REV_C0         ; ASUS
    %ATHR.L1CD% =           L1D2.SYS.ndi,          PCI\VEN_1969&DEV_1083&SUBSYS_83FE1043&REV_C0         ; ASUS
    
    %ATHR.L1D%  =           L1D2.MB.ndi,           PCI\VEN_1969&DEV_1083&SUBSYS_E0001458&REV_C0         ; GIGABYTE
    
    %ATHR.L1D%  =           L1D2.MB.ndi,           PCI\VEN_1969&DEV_1083&SUBSYS_81511019&REV_C0         ; ECS
    %ATHR.L1D%  =           L1D2.MB.ndi,           PCI\VEN_1969&DEV_1083&SUBSYS_10831019&REV_C0         ; ECS
    
    %ATHR.L1D%  =           L1D2.MB.ndi,           PCI\VEN_1969&DEV_1083&SUBSYS_76801462&REV_C0         ; MSI
    
    %ATHR.L1D%  =           L1D2.MB.ndi,           PCI\VEN_1969&DEV_1083&SUBSYS_10831849&REV_C0         ; Asrock
    
    %ATHR.L1D%  =           L1D2.SYS.ndi,          PCI\VEN_1969&DEV_1083&SUBSYS_2AAE103C&REV_C0         ; Pegatron
    %ATHR.L1D%  =           L1D2.SYS.ndi,          PCI\VEN_1969&DEV_1083&SUBSYS_3580103C&REV_C0         ; Pegatron
    %ATHR.L1D%  =           L1D2.SYS.ndi,          PCI\VEN_1969&DEV_1083&SUBSYS_2B01103C&REV_C0         ; Pegatron
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_109C1462&REV_C0         ; Pegatron
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_208D1B0A&REV_C0         ; Pegatron
    %ATHR.L1D%  =            L1D2.SYSShutOn.ndi,    PCI\VEN_1969&DEV_1083&SUBSYS_2AD5103C&REV_C0          ; Pegatron
    
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_3584103C&REV_C0         ; Kitty
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_3585103C&REV_C0         ; Kitty
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_3385103C&REV_C0         ; UMA
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_3386103C&REV_C0         ; DIS
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_1688103C&REV_C0         ; Lauren
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_1689103C&REV_C0         ; Vuitton
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_168A103C&REV_C0         ; Vuitton
     
  19. limeay

    limeay Active Member

    Messages:
    60
    Likes Received:
    1
    GPU:
    Nvidia GTX 1080 Ti
    Code:
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04631025&REV_C0         ; ZR7D
    %ATHR.L1D%  =           L1D2.TxPerf.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_047E1025&REV_C0         ; PAU30
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_048A1025&REV_C0         ; PEW72
    %ATHR.L1D%  =           L1D2.TxPerf.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_050E1025&REV_C0         ; P7YE0
    %ATHR.L1D%  =           L1D2.TxPerf.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_050F1025&REV_C0         ; P7YE0
    %ATHR.L1D%  =           L1D2.TxPerf.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_05131025&REV_C0         ; P7YS0
    %ATHR.L1D%  =           L1D2.TxPerf.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_05141025&REV_C0         ; P7YS0
    %ATHR.L1D%  =           L1D2.TxPerf.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_05151025&REV_C0         ; P7YH0
    %ATHR.L1D%  =           L1D2.TxPerf.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_05161025&REV_C0         ; P7YH0
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_054C1025&REV_C0         ; JM30
    %ATHR.L1D%  =           L1D2.TxPerf.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_054E1025&REV_C0         ; JM30
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_02291025&REV_C0         ; JM31
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_027F1025&REV_C0         ; JM31
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_02801025&REV_C0         ; JM31
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03641025&REV_C0         ; JM31
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_040E1025&REV_C0         ; JV10
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04281025&REV_C0         ; SJV10
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04291025&REV_C0         ; JV10_NL
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_040D1025&REV_C0         ; SJV10_NL
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04601025&REV_C0         ; SJV10_CP
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_045F1025&REV_C0         ; JV10_NL
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03561025&REV_C0         ; ZQ1
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03571025&REV_C0         ; ZQ1
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03581025&REV_C0         ; ZQ1B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03591025&REV_C0         ; ZQ1B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_035A1025&REV_C0         ; ZR7
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_035B1025&REV_C0         ; ZR7
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_035C1025&REV_C0         ; ZR7B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_035D1025&REV_C0         ; ZR7B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_035E1025&REV_C0         ; ZQ2
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03601025&REV_C0         ; ZR8
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03621025&REV_C0         ; ZR8B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03661025&REV_C0         ; ZQ2B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03641025&REV_C0         ; JM31
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03671025&REV_C0         ; ZYA
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_03681025&REV_C0         ; ZYA
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_038B1025&REV_C0         ; ZYB
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_038C1025&REV_C0         ; ZYB
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04121025&REV_C0         ; ZYD
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_040E1025&REV_C0         ; JV10
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04281025&REV_C0         ; SJV10
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04291025&REV_C0         ; JV10_NL
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_040D1025&REV_C0         ; SJV10_NL
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04601025&REV_C0         ; JV10_CP
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_045F1025&REV_C0         ; JV10_NL
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04631025&REV_C0         ; ZR7D
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04641025&REV_C0         ; JV53_CP
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04651025&REV_C0         ; JV53_CP
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04731025&REV_C0         ; SJM70_CP
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04751025&REV_C0         ; SJM70_CP
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04761025&REV_C0         ; SJM70_CP
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_048A1025&REV_C0         ; PEW72
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_051E1025&REV_C0         ; SJV73
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_051F1025&REV_C0         ; SJV73
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05201025&REV_C0         ; JE73
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05211025&REV_C0         ; JE73
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05221025&REV_C0         ; JE73
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05231025&REV_C0         ; JE73
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05241025&REV_C0         ; SJ53
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_052A1025&REV_C0         ; SJ53
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_052D1025&REV_C0         ; ZQE
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_052E1025&REV_C0         ; ZQE
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_052F1025&REV_C0         ; ZQG
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05301025&REV_C0         ; ZQG
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05571025&REV_C0         ; JE41
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_055F1025&REV_C0         ; JE51
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_054B1025&REV_C0         ; HM51
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_054D1025&REV_C0         ; HM51
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_054F1025&REV_C0         ; JM40
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_055B1025&REV_C0         ; JM50
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05711025&REV_C0         ; SJM40
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_056D1025&REV_C0         ; BA70
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_056F1025&REV_C0         ; SJM50
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05731025&REV_C0         ; ZRJ
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05741025&REV_C0         ; SJM40
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_058D1025&REV_C0         ; SJV51
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_058E1025&REV_C0         ; SJV51
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_059C1025&REV_C0         ; JE70
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_059D1025&REV_C0         ; SJV70
    %ATHR.L1D%  =           L1D2.PEGA.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_05391025&REV_C0         ; EIH30
    %ATHR.L1D%  =           L1D2.PEGA.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_053A1025&REV_C0         ; EIH31
    %ATHR.L1D%  =           L1D2.PEGA.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_060C1025&REV_C0         ; EIH30A
    %ATHR.L1D%  =           L1D2.PEGA.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_060D1025&REV_C0         ; EIH31A
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_064E1025&REV_C0          ; Q7YV0
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_064D1025&REV_C0          ; Q7YV0
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_064F1025&REV_C0          ; Q7YS0
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06501025&REV_C0          ; Q7YS0
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06511025&REV_C0          ; Q7YV1
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06521025&REV_C0          ; Q7YV1
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06531025&REV_C0          ; Q7YS1
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06541025&REV_C0          ; Q7YS1
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06631025&REV_C0          ; Q5WP3
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06741025&REV_C0          ; Q7YC1
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06761025&REV_C0          ; Q7YC1
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06851025&REV_C0          ; VA70CR
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06861025&REV_C0          ; VA70CR
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06881025&REV_C0          ; VA70CR
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06891025&REV_C0          ; VA70CR
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_068A1025&REV_C0          ; VA70HR
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_068B1025&REV_C0          ; VA70HR
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_068C1025&REV_C0          ; VA70HR
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_068D1025&REV_C0          ; VA70HR
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06961025&REV_C0          ; VA50_CM
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06981025&REV_C0          ; VG50_CM
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_06901025&REV_C0          ; Q5WT6
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05761025&REV_C0          ; BA50
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_07151025&REV_C0          ; ZQZ
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_07221025&REV_C0          ; BA50HC(CR)
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_07231025&REV_C0          ; BA50HC(HR)
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_073D1025&REV_C0          ; EG70_BZ
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_073E1025&REV_C0          ; EG70_BZ_PX
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_07561025&REV_C0          ; ZRP
    %ATHR.L1D%  =            L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_07571025&REV_C0          ; ZRP
    
    %ATHR.L1D%  =           L1D2.WOLNone.ndi,      PCI\VEN_1969&DEV_1083&SUBSYS_048F1028&REV_C0         ; Dell_Avenger
    %ATHR.L1D%  =           L1D2.WOLNone.ndi,      PCI\VEN_1969&DEV_1083&SUBSYS_04901028&REV_C0         ; Dell_Voyager
    %ATHR.L1D%  =           L1D2.WOLNone.ndi,      PCI\VEN_1969&DEV_1083&SUBSYS_04911028&REV_C0         ; Spector
    %ATHR.L1D%  =           L1D2.WOLNone.ndi,      PCI\VEN_1969&DEV_1083&SUBSYS_04C81028&REV_C0         ; Alienware
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04A61028&REV_C0         ; DJ2_MV
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_049E1028&REV_C0         ; DJ2_AMD
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_049F1028&REV_C0         ; DJ2_CP_UMA
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04A01028&REV_C0         ; DJ2_CP_DIS
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04371028&REV_C0         ; Miso
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04461028&REV_C0         ; Panerai
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_04841028&REV_C0         ; UMA
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_051F1028&REV_C0         ; UMA1
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05201028&REV_C0         ; UMA2
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05211028&REV_C0         ; UMA3
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05221028&REV_C0         ; Discrete1
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05231028&REV_C0         ; Discrete2
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05241028&REV_C0         ; Discrete3
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05481028&REV_C0         ; Olympic
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_054B1028&REV_C0         ; Princeville
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05501028&REV_C0         ; Avenger II
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05511028&REV_C0         ; Voyager II
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05521028&REV_C0         ; Spector II
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_057B1028&REV_C0         ; Voyager II
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_05801028&REV_C0         ; Voyager II
    
    %ATHR.L1D%  =           L1D2.TxPerf.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_397917AA&REV_C0        ; PIWG1/2/3
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_397B17AA&REV_C0        ; PAWGx
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_398317AA&REV_C0        ; PAW10/20
    %ATHR.L1D%  =           L1D2.LVOn.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_21EC17AA&REV_C0         ; Davis
    %ATHR.L1D%  =           L1D2.LVOn.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_21ED17AA&REV_C0         ; Davis
    %ATHR.L1D%  =           L1D2.LVOn.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_21EE17AA&REV_C0         ; Payton
    %ATHR.L1D%  =           L1D2.LVOn.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_21EF17AA&REV_C0         ; Payton
    %ATHR.L1D%  =           L1D2.LVOn.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_21F017AA&REV_C0         ; Payton
    %ATHR.L1D%  =           L1D2.LVOn.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_21F117AA&REV_C0         ; Payton
    %ATHR.L1D%  =           L1D2.LVOn.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_21F217AA&REV_C0         ; Payton
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_397717AA&REV_C0        ; Y490
     
  20. limeay

    limeay Active Member

    Messages:
    60
    Likes Received:
    1
    GPU:
    Nvidia GTX 1080 Ti
    Code:
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08611854&REV_C0        ; QLH
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08621854&REV_C0        ; QLH
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08631854&REV_C0         ; QLH
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08641854&REV_C0         ; QLH
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08651854&REV_C0         ; QLH
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08661854&REV_C0         ; QLA
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08671854&REV_C0         ; QLA
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08681854&REV_C0         ; QLA
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08691854&REV_C0         ; QLC
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08701854&REV_C0         ; QLC
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08711854&REV_C0         ; QLC
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08891854&REV_C0         ; QLM
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08901854&REV_C0         ; QLM
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08911854&REV_C0         ; QLM
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08921854&REV_C0         ; QLM
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08961854&REV_C0         ; LG2
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08971854&REV_C0         ; LG2
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08981854&REV_C0         ; LG2
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_08991854&REV_C0         ; LG4
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_09001854&REV_C0         ; LG4
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_09011854&REV_C0         ; LG4
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_09021854&REV_C0         ; LG7
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_09031854&REV_C0         ; LG7
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_09041854&REV_C0         ; LG7
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_09061854&REV_C0         ; A430
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_09071854&REV_C0         ; A430
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_09081854&REV_C0         ; A430
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_17911854&REV_C0         ; A420
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_17921854&REV_C0         ; A430
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_17931854&REV_C0         ; A430
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_17981854&REV_C0         ; LG2B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_17991854&REV_C0         ; LG2B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_18001854&REV_C0         ; LG2B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_18011854&REV_C0         ; LG4B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_18021854&REV_C0         ; LG4B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_18031854&REV_C0         ; LG4B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_18041854&REV_C0         ; LG2B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_18051854&REV_C0         ; LG2B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_18061854&REV_C0         ; LG4B
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_18071854&REV_C0         ; LG4B
    
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_1650103C&REV_C0         ; Zidane UMA
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_1651103C&REV_C0         ; Zidane SG
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_3595103C&REV_C0         ; KID
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_3596103C&REV_C0         ; KID
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_1851103C&REV_C0         ; Inventec / HP
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_1852103C&REV_C0         ; Inventec / HP
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_1853103C&REV_C0         ; Inventec / HP
    
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FDD11179&REV_C0         ; TE7
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FFD61179&REV_C0         ; TZ6
    %ATHR.L1D%  =           L1D2.TOSHIBA.ndi,      PCI\VEN_1969&DEV_1083&SUBSYS_FF1E1179&REV_C0         ; WS2
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FCB01179&REV_C0         ; TZ6
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FC501179&REV_C0         ; BLF
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FCD01179&REV_C0         ; TE5
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FCC01179&REV_C0         ; BU5
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FD521179&REV_C0         ; BLE
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FDD21179&REV_C0         ; BU4
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FD401179&REV_C0         ; BU4
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FDD01179&REV_C0         ; TE4
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FD501179&REV_C0         ; BLG
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB901179&REV_C0         ; BU8
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB911179&REV_C0         ; BU8D
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB921179&REV_C0         ; BU8D
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FCD31179&REV_C0         ; BY5/BY5D
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB551179&REV_C0         ; BY6
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB561179&REV_C0         ; BY6D
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FCD21179&REV_C0         ; BY3
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FCD41179&REV_C0         ; BY3D
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FCD51179&REV_C0         ; BY3D
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FC551179&REV_C0         ; BY4
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FC561179&REV_C0         ; BY4D
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FC571179&REV_C0         ; BY4D
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB501179&REV_C0         ; BY3C
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB511179&REV_C0         ; BY3G
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB521179&REV_C0         ; BY3G
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB801179&REV_C0         ; BY4C
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB811179&REV_C0         ; BY4G
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB821179&REV_C0         ; BY4G
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FCC51179&REV_C0         ; KZ1
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FC421179&REV_C0         ; BY1
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FAB31179&REV_C0         ; BY2D
    %ATHR.L1D%  =           L1D2.PWMAll.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FB721179&REV_C0         ; BYD
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_FC661179&REV_C0         ; Celtic
    
    %ATHR.L1D%  =           L1D2.SONY.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_9080104D&REV_C0         ; V050
    %ATHR.L1D%  =           L1D2.SONY.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_9081104D&REV_C0         ; V050
    %ATHR.L1D%  =           L1D2.WOLNone.ndi,      PCI\VEN_1969&DEV_1083&SUBSYS_908A104D&REV_C0         ; Z40/50
    %ATHR.L1D%  =           L1D2.SONY.ndi,         PCI\VEN_1969&DEV_1083&SUBSYS_908D104D&REV_C0         ; Z40/50BR
    
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0872152D&REV_C0         ; LG
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0873152D&REV_C0
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0875152D&REV_C0
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0876152D&REV_C0
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0877152D&REV_C0
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0878152D&REV_C0
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0883152D&REV_C0         ; SW6H
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0884152D&REV_C0         ; SW6H
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0880152D&REV_C0         ; SWH
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0913152D&REV_C0         ; JW1
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0914152D&REV_C0         ; JW1
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0915152D&REV_C0         ; JW1
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0916152D&REV_C0         ; JW1
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0917152D&REV_C0         ; JW1
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0952152D&REV_C0         ; TWC
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0953152D&REV_C0         ; SWH
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0988152D&REV_C0         ; JW8
    
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_10E717C0&REV_C0         ; M51
    
    %ATHR.L1D%  =           L1D2.ndi,              PCI\VEN_1969&DEV_1083&SUBSYS_0DBE105B&REV_C0         ; Clone
    %ATHR.L1D%  =           L1D2.ShutOn.ndi,       PCI\VEN_1969&DEV_1083&SUBSYS_0E2D105B&REV_C0         ; Livebox
    %ATHR.L1D%  =           L1D2.ECS.ndi,          PCI\VEN_1969&DEV_1083&SUBSYS_0D83105B&REV_C0         ; Foxconn   
    
    %ATHR.L1D%  =           L1D2.MB.ndi,           PCI\VEN_1969&DEV_1083&SUBSYS_28031565&REV_C0         ; BIOSTAR
                                
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091                    ; L1F
    
    %ATHR.L1F%  =            L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_85071043             ; ASUS
    %ATHR.L1F%  =            L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_200F1043             ; ASUS
    
    %ATHR.L1F%  =            L1F.MB.ndi,            PCI\VEN_1969&DEV_1091&SUBSYS_81611019             ; ECS
    
    %ATHR.L1F%  =            L1F.MB.ndi,            PCI\VEN_1969&DEV_1091&SUBSYS_E0001458             ; GIGABYTE
    
    %ATHR.L1F%  =            L1F.MB.ndi,            PCI\VEN_1969&DEV_1091&SUBSYS_10911849             ; Asrock
    
    %ATHR.L1F%  =            L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_AA5D1462              ; MSI
    
    %ATHR.L1F%  =            L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_2AD5103C            ; Pegatron
    %ATHR.L1F%  =            L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_2AE0103C                ;
    
    %ATHR.L1F%  =            L1F.ShutOn.ndi,        PCI\VEN_1969&DEV_1091&SUBSYS_05001025              ; JE40-CR
    %ATHR.L1F%  =            L1F.ShutOn.ndi,        PCI\VEN_1969&DEV_1091&SUBSYS_06431025              ; JV42-HR
    
    %ATHR.L1F%  =            L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_397917AA              ; Lenovo
    %ATHR.L1F%  =            L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_397817AA              ;
    %ATHR.L1F%  =            L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_397C17AA              ;
    %ATHR.L1F%  =            L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_397717AA              ; Y490
    
    %ATHR.L1F%  =           L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_05481028                ; Olympic
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_054B1028                ; Princeville
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_055B1028                ; M13
    %ATHR.L1F%  =           L1F.ShutOn.ndi,        PCI\VEN_1969&DEV_1091&SUBSYS_055C1028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_055D1028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_055E1028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_055F1028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_05601028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_05611028                ; M13
    %ATHR.L1F%  =           L1F.ShutOn.ndi,        PCI\VEN_1969&DEV_1091&SUBSYS_05621028                ; M13
    %ATHR.L1F%  =           L1F.ShutOn.ndi,        PCI\VEN_1969&DEV_1091&SUBSYS_05631028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_05641028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_05651028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_05661028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_05671028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_05681028                ; M13
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_057E1028                ; DMB40
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_057F1028                ; DMB40
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_058F1028                ; Z5_UMA
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_05901028                ; Z5_Discrete
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_05D91028                ; Titan
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_05DA1028                ; Titan
    %ATHR.L1F%  =           L1F.ShutOn.ndi,        PCI\VEN_1969&DEV_1091&SUBSYS_05E71028                ; Titan
    %ATHR.L1F%  =           L1F.ShutOn.ndi,        PCI\VEN_1969&DEV_1091&SUBSYS_05E81028                ; Titan
    
    %ATHR.L1F%  =           L1F.ndi,                 PCI\VEN_1969&DEV_1091&SUBSYS_17951854                ; QLC
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_17961854                ; QLC
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_17971854                 ; QLC
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18081854                 ; QLGA
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18091854                ; LG3
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18101854                ; LG3
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18111854                ; LG3
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18121854                ; LG5
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18131854                ; LG5
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18141854                ; LG5
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18151854                ; LG2C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18161854                ; LG2C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18171854                ; LG2C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18181854                ; LG4C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18191854                ; LG4C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18201854                ; LG4C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18211854            ; LG2C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18221854            ; LG2C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18231854            ; LG2C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18241854            ; LG4C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18251854            ; LG4C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18261854            ; LG4C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18271854            ; LG2C
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_18281854            ; LG4C
    
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_20D61B0A                ; Pegatron
    %ATHR.L1F%  =           L1F.ndi,               PCI\VEN_1969&DEV_1091&SUBSYS_20FA1B0A                ; Pegatron
    %ATHR.L1F%  =           L1F.PEGA.ndi,           PCI\VEN_1969&DEV_1091&SUBSYS_01501B0A                ; Pegatron
    %ATHR.L1F%  =           L1F.PEGA.ndi,          PCI\VEN_1969&DEV_1091&SUBSYS_01571B0A                ; Pegatron
     

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