The AMD Ryzen All In One Tread /Overclocking/Memory Speeds & Timings/Tweaking/Cooling Part 2

Discussion in 'Processors and motherboards AMD' started by vbetts, Sep 24, 2018.

  1. -Tj-

    -Tj- Ancient Guru

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  2. gerardfraser

    gerardfraser Ancient Guru

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    Normal with Single CCD,two CCD back to regular normal what people are used to speed.
    AMD says:has no affect on performance.

    quote from review
     
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  3. Webhiker

    Webhiker Master Guru

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  4. Mr. Sunshine

    Mr. Sunshine Master Guru

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    Unless he's trolling...... trying anyways.
     

  5. gerardfraser

    gerardfraser Ancient Guru

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    He is asking a real question,crap you people.
     
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  6. gerardfraser

    gerardfraser Ancient Guru

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    Deleted video ,NFSW
     
    Last edited: Oct 20, 2019
  7. Clouseau

    Clouseau Ancient Guru

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    After watching this vid:
    and then seeing gerardfraser's post, I went for broke down a rabbit hole that I eventually was met with a very unconventional final timing for primaries. Final result was 16-16-11-13-24-40. CLD0 VDDG .975v, SOC offset -.01875, DRAM 1.4200v. preliminary results are:

    Testmem5
    [​IMG]

    Aida64 Cache & Memory
    [​IMG]

    Corona
    [​IMG]

    Cinebench 15
    [​IMG]

    The Synthetic benches do not really show much of an improvement if any but the actual performance uplift is there and noticeable. Still not convinced is completely stable yet but have not experienced any hiccups either. More game time is needed.

    Settings:
    EDIT: Terrible with exact names so bios screens:
    [​IMG]
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    There must be a hardware limitation somewhere and I still do not know enough about ram because still cannot break past 63.6 for latency; best I can do.
     
    Last edited: Oct 20, 2019
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  8. -Tj-

    -Tj- Ancient Guru

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    Last edited: Oct 20, 2019
  9. Clouseau

    Clouseau Ancient Guru

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    ^Cannot remember exactly where but it was stated that with one CCX(one cpu chipelt) there was only "1/2" bandwidth communication with DRAM writes. Therefore with the 3900X having two chiplets there is no write "penalty".
     
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  10. user1

    user1 Ancient Guru

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    I have kind of a crazy question, does anyone know if ryen 3000 has a 1:4 fclk:mclk ratio, ie if you are running 1000mhz fabric, you would hit a 4000mt/s memory rate. The thought came to mind after reading about the latency hit from async mode, and i remembered on some older platforms would let you run the memory at 2x the bus speed and not suffer a latency hit(p45 running 1600mt/s ddr3 on 400mhz fsb). while it may not be very useful, it would be interesting to see if running an even ratio would have any effect on the latency hit, might be something for someone say running a 4800mt/s memory kit and beyond to checkout if they are feeling adventurous.
     
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  11. gerardfraser

    gerardfraser Ancient Guru

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    You have some good settings,maybe nothing you can do about the latency.It could just be the newer the motherboard BIOS with fixes is the problem.I would try older BIOS for some fun and see how it goes.
     
  12. Kool64

    Kool64 Master Guru

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    At 3800 and above (on auto) it goes 2:1 though you can manually force it to go 1:1 but I've not heard of anyone achieving a 2k IF speed.


    [​IMG]
     
  13. user1

    user1 Ancient Guru

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    from what i understand its such that when in synchronous mode it would be fclk=uclk=mclk , but if the uclk divider is enabled (to achieve high memory frequency like shown) then the uclk(memory controller speed) is half the memory speed, resulting in a very low uclk that is decoupled from the fclk. what im suggesting is the fclk still equals the uclk but the divider remains enabled, theoretically if the fclk is still equal to the uclk, there would be no need for buffering,potentially removing the latency penalty that is observed (at least as i understand it) ,

    so instead of doing something like 1900 fclk : 1000uclk: 2000(4000mt/s)mclk as what would normally happen if going over 3733mt/s ,
    it would be 1000 fclk : 1000 uclk : 2000(4000mt/s) mclk , this would obviously have massive bandwidth drawbacks. but if you were say running 5GT/s-6GT/s ddr4 it might be lower latency than async mode.
     
    Last edited: Oct 21, 2019
  14. Jawnys

    Jawnys Member Guru

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    new 3733 tweak. i cant make it to 3800 stable on my 3900x with 4 stick, im using asrock x570 steel legend, im happy with my tweak so far, great bandwith in aida65
    https://imgur.com/EiVpUEA
     
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  15. Clouseau

    Clouseau Ancient Guru

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    In the video linked in my previous post, the latency penalty is mentioned; ~9ns. Some of the benches showed that even with the penalty it benched in the top performing group. So not as bad as it sounds. It was suggested by AMD that fiddling with the timings is all that may be needed to overcome the latency hit.
     

  16. Jawnys

    Jawnys Member Guru

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    for sure you can reduce the latency hit, i can get 71 ns on 4000 mhz, definitly not bad, maybe if i cann push to 4200-4400 with decent timing i can go under 70 ns
     
  17. Jawnys

    Jawnys Member Guru

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  18. Clouseau

    Clouseau Ancient Guru

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    Well sad news...those settings have now been confirmed as not stable :(

    I have not thrown in the towel but rather have embarked on a different route to the top. I have never bothered to take the time to see the influence each particular timing (after the primaries) influences bandwidth and latency. Going to take a long time but will finally see what the actual gains or regressions are one setting at a time (benchmarks run after stability is achieved with Testmem5. Will also see what individual or group of settings require a voltage increase to gain stability. Man is it painful on setting a baseline. The out-of-the-box timings as listed on the Typhoon Burner report, converting some ns times to cycles, makes me really appreciate what just tackling the low hanging fruit accomplishes performance wise. Out of the box timings as dictated by the information in the spd for F4-3600C16D-16GTZ even when run at 3800 was excruciating. It took over 30 minutes to complete a run in Testmem5. The results in Aida was lackluster but the latency of 65.3 was not bad. CB R20 score was 5089 multi and 519 single. More to come if I do not bang my head against the wall too hard too many times.
     
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  19. 386SX

    386SX Maha Guru

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    Still fiddling with RAM timings. I am one step before rock stable, I can almost feel it. :D

    What bugs me is one damn single error in Testmem 0.12 with 1usmus v2 profile while doing a run of 5 cycles. Before it happened in test 1 every cycle. I then recalled @Clouseau 's tip of setting voltages to 1.38 or 1.41V, 1.41V got me into this. Thanks so far.
    Now I get always one error, either in test 10 (1 time only) or 11 / 12.

    Any idea what I may change to solve this? ProcODT other than 53.3 doesn't boot. RTT nom is 34.3 (RZQ/7), park is RZQ/5 and wr disabled. SOC is set to manual 1.025V which results in 1.018V effectively.

    And one question to the SSE field in Testmem ... what value should be considered average? With 14-14-14-14-28-42 I saw mostly about 12.8 seconds per Gb. With 14-13-14-13-28-42 I see values hovering a lot, ranging from 18 to 55, mostly at 20 - 25. All with 3200MHz and timings taken mostly from custom fast profile with Typhoon import.
     
  20. Clouseau

    Clouseau Ancient Guru

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    AddrCmdSetup, CsOdtSetup, and CkeSetup try setting these to either 0 or 1. The resistances of the other four that ended up working for me was 24-24-24-24. Only on the last bios before switching hardware did 20-20-20-20 work. Then again ProcODT for me was the value right below 53.3...think it was 48. Magic stability settings for me was 14-14-15-14. That is how it worked out for me until a bios update came and then was able to run 14-14-14-14.

    Also, same with current Ryzens, Trfc has a huge influence. Next is FAW.
     
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