PCIe 6.0 Specification To be Finalized in 2021

Discussion in 'Frontpage news' started by Hilbert Hagedoorn, Nov 5, 2020.

  1. Hilbert Hagedoorn

    Hilbert Hagedoorn Don Vito Corleone Staff Member

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    While you are really diggin' that PCI-Express 4.0 slot of yours, the design for 5.0 has been finished, and wait for it, yep ... PCIe 6.0 is in full development and is to be finalized as a standard i...

    PCIe 6.0 Specification To be Finalized in 2021
     
  2. tsunami231

    tsunami231 Ancient Guru

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    we barely have 4.0 on MB and CPU...

    Storage that acual uses that available speed would be amazing if they didnt cost more then some gpu's at 2tb.

    Do any current GPU even come close to saturating 3.0? let alone 4.0?
     
  3. Undying

    Undying Ancient Guru

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    If multi gpus ware not dead pcie4 would be saturated pretty quckly.
     
  4. jbscotchman

    jbscotchman Ancient Guru

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    Get back to me in 8 years. No offense Hilbert. As the saying goes: "Don't shoot the messenger."
     

  5. wavetrex

    wavetrex Ancient Guru

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    Seems that everyone on the internet commenting about PCI-e 4.0 is useless keep forgetting about the newly introduced feature "Smart Memory Access" where CPU has direct 64-bit mapped access to entire GPU memory.

    I don't know exactly what it does, but it seems to me that the CPU could have parts of a game loaded straight into the GPU, and then just instruct the GPU to "use" that portion of VRAM.
    And swap stuff in an out in the background while the GPU is doing other stuff.

    Sounds like the kind of scenario where I/O bandwidth increase can help.

    ---
    I imagine future CPU/GPU/SSD would be treated like one giant pool of memory, with ability to execute code and read/write data straight of any of them.
    It would be like a giant caching structure:

    L1 cache - Inside the CPU cores
    L2 cache - Very near the CPU cores
    L3 cache - On the CPU die
    L4 cache - The RAM and VRAM
    L5 cache - PCI-e SSD
    Base storage ?.... the internetz.

    Games could stream stuff in and out as needed, only using the SSD as a cache.
    Isn't there a game which already does that ? Hmm... something with airplanes I think.
     
  6. DmitryKo

    DmitryKo Master Guru

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    PCIe 5.0 / 6.0 roadmap has already been discussed in earlier threads, there is nothing much to add.

    PCIe 6 Announced
    PCI Express 6.0 Specification Revision 0.3
    PCIe 6.0 Specification finalized in 2021 and 4 times faster than PCIe 4.0



    We already have SSD controllers that stretch PCIe 4.0 bandwidth to the maximum 8 Gbyte/s allowed by 4-lane M.2 form-factor.

    Phison Going For 7GB/sec Storage on PCIe 4.0 with PS5018-E18
    Samsung 980 PRO M.2 gets PCIe Gen4 and performance up to 6,500 MB/s
    Review: Samsung 980 Pro 1TB NVMe SSD
    Lexar hits 7 GB/s with new M.2 PCIe 4.0 SDD


    16-lane PCIe 6.0 bandwidth of 126 GByte/s matches dual-channel DDR5-8400 system memory and this would allow faster swapping of game resources with GPU video memory.
     
    Last edited: Nov 7, 2020
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  7. DmitryKo

    DmitryKo Master Guru

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    "Smart Memory Access" looks like PCIe Resizeable BAR with 64-bit BAR registers and BAR Size that would encompas entire local video memory, to map it into CPU's 64-bit virtual address space.
    Current GPU drivers use much smaller window, typically 256 Mbyte as inherited from 32-bit operating systems.


    But what you describe above would require either common cache coherence protocols over PCIe 5.0, or proprietary cache-coherent buses in HPC boards with socketed GPUs. So far this has only been implemented in supercomputers based on IBM POWER8+ processors and NVidia Tesla accelerators connected with NVLink bus, the upcoming Cray El Capitan supercomputer with Shasta architecture, where AMD EPYC 'Trento' Zen3 processors and Radeon 'MI200' CDNA accelerators are interconnected with Infinity Fabric bus (AKA Infinity Architecture 3), and the upcoming Cray Aurora supercomputer, where Intel Xeon 'Sapphire Rapids' processors and Xe-HPC 'Ponte Veccio' accelerators are connected with CXL based 'Xe Link' protocol over PCIe 5.0 bus.
     
    Last edited: Mar 24, 2021
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  8. kapu

    kapu Ancient Guru

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    Another generation of gpus should saturate 3.0. But that's far from 4.0....
     
  9. wavetrex

    wavetrex Ancient Guru

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    Ah !
    So it does exist.

    Just like every other fancy feature, it was first implemented on the enterprise and then eventually trickled down to consumer space.

    "The future is bright" (and fast)
     
  10. DmitryKo

    DmitryKo Master Guru

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    Yes, surely technology from Cray supercomputers will trickle down to consumers eventually. It only took 25 years for a high-end Cray Y-MP configuration with 8 processors, 32 GBytes of RAM, and 1 GByte/s solid-state disk to trickle down to my current home PC. :D
     

  11. boe

    boe Master Guru

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    I'd be so much more excited if Intel and AMD announced they'd be supporting twice the number of PCIe lanes on standard processors and chipsets next year. Unless you get a server type processor and motherboard, you've already gone over the number of lanes your system supports if you put in 2 video cards. Sure they make some bridge type chips but there is a performance gap. I have a fast video card, a high end raid card and a 40g nic. Combine that with onboard sound, on board nic, and other standard ports as well as ssd slot, you've gone way over the PCIe lane allotment.
     

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