Discussion in 'Videocards - AMD Radeon' started by OnnA, Jul 9, 2016.
a year or two.. you get what you paid it does not matter
RGT videos should be played at 1.25x speed, because he is rumbling to reach 10 minutes mark.
And while most of his videos are waste of time, it is bit less wasteful when played faster.
To sum up 12 minutes, there is 30s of "valuable" content.
AMD's way of doing rays can be more or less optimized. (Surprise? *-*)
Radeon Boost is going to be used. (Surprise? *-*)
I am not surprised his video had really no value above TV running in background to create some noise.
Well this and.... that anything can be borked to run badly... *cough* NV-Sponsored *cough* Control.
And that optimized wave32 is the way to go ? Actually the most important are the things posted on github --- what and how to optimize for AMD DXR. Rest I agree -- is just blabber to cash on YT, but hey, at least he does something useful compared to all the other YT-"celebrities"
"Ask AMD's GPU chief about the Radeon RX 6700 XT on The Full Nerd today! See you at 3 pm ET / noon Pacific"
Everyone go and ask for FidelityFX Super Resolution XD
Here's the interview
No IPC uplift in this one interesting indeed.
299-329€ o_0 That's better (Corrected ).
PowerColor leaks RX 6700 6GB
And its gone!
having 8gb card, seems like a downgrade
I don't think it's a 1440P card
Yeah current price dumbe. But tbh if it was around the same price as 3060 ti it would be fine. Even if it lost in RT. But alas it ain't
AMD Announces new wave of reference MSRP RX 6x00 cards
Lucky Me. I do not use autoplay on youtube. Frank Azor Jumps on screen immediately.
AMD Chiplet GPU Patent App - Active Bridge Chiplet with Integrated Cache
AMD is continuing to develop their MCM-GPU tech, with their latest patent application detailing an active bridge die with an on-board GPU cache. What this means for future GPUs:
Chiplet GPUs are 100% coming
Chiplet GPUs will utilize a shared L3 cache as communication between chiplets
These chiplets are connected via an embedded bridge (much like Intel EMIB) = very low latency and low power (similar to on-chip latency and power)
Chiplet GPU L3 (Infinity) Cache will reside on the interconnect bridge itself, meaning that the bridge will be an active interposer
The diagrams illustrate a very long and thin L3 interconnect chiplet, however in reality this chiplet will probably be more rectangular than shown, as the GPU chiplets will likely be placed in a x * 2 grid pattern to save space.
Credits to Redditor Su Dilligence >
Now theres a chance of RDNA3 being chiplets, the missing piece is complete.
Will require larger IF than 128MB. Because each compute/render chiplet has only few memory channels for itself and L2 in between GPU chiplets needs synchronization via L3.
But it will be reasonably cheap when it has its own chiplet. May be even interesting to see effect of having extra 512MB of L3.
Now that could be interesting and cool.
isn't rdna3 planned for this year ?
It's usually 18 month between releases so with both NV and AMD launching late last year, probably looking at March April 2022 at earliest.