Discussion in 'Frontpage news' started by Hilbert Hagedoorn, Nov 6, 2018.
Intel right now....
So glad I'd waited, I was tempted to go Zen+ with a 2700X build, now I may build two such rigs for my two gaming rigs....
Which means it's time to go with at least 8 cores next year as DDR4 prices are reportedly falling. I hope a proper GPU to replace the rx480 8GB maybe too.
Oh I can't wait for reviews of Zen2. I hope they release it sometime around the next GPU series of both AMD and Nvidia so I can make a whole new nice build.
Happy to see that 7nm is on schedule. Keep it up AMD!
Zen2 looking very nice ! Now we need Navy high end GPU news
That 1.7x figure on cost would be assuming they can maintain current 90%+ yields, which when producing monolithic dies, you don't get that high a yield. Be lucky to see 20% on a fully functional die at these sizes. Suddenly that cost per chip starts to skyrocket.
everybody is talking about Zen2 here, but im more interested over Radeon Instinct Mi60, because is the Vega Frontier version of Vega20, @1.80GHz is 16% more clocks than actual VEGA64 and 4096-bit bus HBM@1GHz, is over the double Memory Bandwidth than VEGA64, no bottlenecks? and less power draw, that is interesting
Hahaha if i ever see a ferarri with a matress strapped on the ceiling and chairs etc stuffed on the back or something i can then die happy
Vega still has some inherent limitations which hold back clock. Navi should not have them. And considering AMD fits double Amount of cores into CPU with likely same/similar TDP and improve performance... One can expect that their 50% power consumption in comparison to last gen holds true.
That means Navi will not be held back by TDP as was Fiji and Vega. (Unless it is performing ~3 times as good as Vega.)
I hope that AMD starts consumer Chips with some awesome APU for notebooks. This greatly improved power efficiency grants as many wins there as in Server business. Maybe something like 4C/8T ~4.0GHz + 20x Navi CUs. And they could throw 2x 8GB HBM2 stacks on package too as main memory (super light and powerful 12'' +most of space used for battery). Or 1x 4GB HBM2 + 2x 4GB DDR4 and form 1st brutal HSA device for consumer market.
Yes i am waiting for new components hope they release them soon my old desktop need some upgrade
Processor enhancements including up to 64 “Zen 2” cores, increased instructions-per-cycle1 and leadership compute, I/O and memory bandwidth2.
On the footnotes
"1. Estimated increase in instructions per cycle (IPC) is based on AMD internal testing for “Zen 2” across microbenchmarks, measured at 4.53 IPC for DKERN +RSA compared to prior “Zen 1” generation CPU (measured at 3.5 IPC for DKERN + RSA) using combined floating point and integer benchmarks."
I don't know what DKERN+RSA is, but I like it, because it's bigger numbers in Zen2
(Yeah I know... I googled it, still not a pro on that matter.)
Hmm, that's a pretty difficult statement to parse.
Just looking at the numbers that would imply a ~30% increase in IPC in that particular workload. Then again we know that Zen 2 doubled the theoretical AVX performance and if that makes up a major part of said workload the non-AVX IPC increase may not be nearly as large.
The general architectural changes mentioned in the slides seem significant though, so I'd bet on a larger increase than we saw from Zen to Zen+. Finger crossed for 10%+!
Yes, more than likely that's why
I want to see the ryzen chips, i think this time they will be different than the Epyc ones
That IPC test is purely in-cache ipc.
we will need to see single core cinebench and such testing to get a fair idea.
I have to admit I'm very uncertain myself at this point.
One of the AMD slides claimed that the IO chiplet design had "improved latencies and power", which I take to mean "reduced" when it comes to latency. Of course there's no telling what kind of latency they're talking about here, it might not refer to memory at all and even if it does it could mean improved compared to cross-CCX latency. *shrug* It's all marketing stuff so likely to show the ideal case.
That said I can quite easily imagine Ryzen 3k ending up with the same 7nm 8-core CPU chiplet as Rome and a different IO die. It would allow AMD to keep reusing the same 7nm dies and it's presumably cheaper to design different IO dies on 14nm than a monolithic Ryzen 3k SoC on 7nm, given that the IO doesn't scale as well.
I suppose it primarily comes down to
whether the IO, especially memory, latency of the CPU + IO chiplet is competitive or improved compared to a monolithic design for lower core-counts and
whether the CPU chiplet used in Rome can run at higher clocks/voltage suitable for desktop computing without any design tweaks as well as
cost/size constraints of each approach.
If the CPU chiplet will require a major redesign for desktop usage regardless I could well see a monolithic design for Ryzen 3k.
The again a two "high performance" 4-core CPU chiplets and separate IO design might also make sense in that scenario.
Bah, too many options at this point! It's been a long time since I felt as invested in tech news as I am today.
AMD Gimped the Tesla V100
From my understanding the Tensor cores can only be used in certain circumstances, in this case AMD picked the one where Tensor cores couldn't be used to show their advantage. So cherry picked really, after all why would you pick the circumstances where your competitor has an edge when show casing your own product?
Tensor cores apparently don't work in FP32, they only work using using in FP16 or in a mixed FP16 and FP32 workloads where the tensor cores do the 16FP and the card processes 32FP, thus the test is litigate, but only if you use only FP32 instructions.