Intel's Latest Process and Packaging Roadmap

Discussion in 'Frontpage news' started by Mda400, Jul 26, 2021.

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  1. Mda400

    Mda400 Master Guru

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    Just came across this Intel newsroom article intel posted today, while looking at the Wikipedia page for Alder Lake.

    https://www.intel.com/content/www/u...ccelerates-process-packaging-innovations.html

    They are naming their processes "Intel #" from their definition of nanometer down to angstrom.

    After "Intel 3", RibbonFET (Intel's name for gate-all-around FET) and PowerVIA - a power delivery system, where power will be fed into the chip from the back-side, while the front-side will be used primarily for data routing. PowerVia will optimize signal transmission by eliminating the need for power routing on the front side of the wafer. The end result according to Intel is higher density and a significant reduction in voltage droop.
     
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  2. fantaskarsef

    fantaskarsef Ancient Guru

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