An Introduction to HBM - High Bandwidth Memory Article

Oh shiet. Good thing you bumped this, I didn't notice it yesterday. I love articles like this.

 

Great article HH. Very interesting. Hope this can help AMD pull themselves out of the hole. Can't wait to see the numbers.

 

Thank you Hilbert, good stuff!

 

Excellent article Hilbert , thank you.

 

Idk, I feel like it's going to be more complex then DX12 = stacked memory. It will probably depend on the game, the implementation, if it will be fully stacked or just some resources, etc.

But yeah overall it should be a net benefit.

 

Cooling will be a *** (female-dog)

AMD is all about 4k lately. So I would expect 8GB version.

 

With D3D12 exposing streaming assets, like virtualized textures, future games and apps shouldn't need to preload everything in the video memory and--in theory--GPUs won't need gobs of local memory, just a small amount of really fast pool (HBM). We shall see.

PCI-E 4.0 is also on the horizon...

 

So....... Pascal will have HBM2? Shut up and take my father's money!

 

To me since it being the first time using HBM and it is the first generation of the technology there was a chance of a limitation like this. However I thought the limitations would be at least no more than 8gb. But Couldn't AMD stack two groups of 4 1gb chips to get 8GB and they could make 8gb cards that way? Or I am I missing something that wouldn't work like that.

 

I'm excited to see the advancements to this new technology. Eager to see the new cards perform.

 

The data who need to be stored / accessed faster, will go the HBM, the large data pool, can be stored on the Dram. Like shown on the slide page 2, you have a complete versatile memory system.

With HSA and other system like that, remember that the cpu and gpu can access every pool memory of the system. ( basically the CPU could store data directly in the gpu HBM memory stack and the gpu could directly treat thoses data, in the other way, the gpu could store the data in the system memory and the cpu could access thoses data directly ).

This is even more important when we speak about HPC, with multiples blades of cpu / gpu's and high amount of them.

 

Just a quick question, isn´t HBM going to create an heat problem in the GPUs? With all the chips stacked on top of each other, isn´t this going to trap heat inside them, leading to higher temps or lower clocks, or i´m seing this the wrong way?

Anyway, cool stuff. Can´t wait to see AMD´s next GPU with this "super" memory inside.

 

From the article:
"For those wondering, will the HBM DRAM blocks be much higher (in physical size) then say a GPU ? E.g. isn't the HBM DRAM package like a skyscraper and the GPU or CPU the size of a house ? We asked AMD, and the answer was no, the difference looks blown up in the screenshots and diagrams, but the real-world difference is not big enough to make a substantial or relevant enough difference. Also mind you that both the GPU and DRAM packages will get materials around them. Thus concerns like heat conduction versus coolers are not a relevant issue, according to AMD."

I was one of those people wondering how they would manage the different heights of DRAM and GPU core, but they're gonna have packaging material around those components to make it all the same height by the sound of it. If that's the case then I hope that material has good conductivity properties otherwise GPU cooling of the core could be compromised. I have no idea what material they'll use, maybe they'll even use a metal cap like intel, and we know the heat problems associated with the use of the metal cap and poor quality interface material between the chip and the metal cap. Fingers crossed they don't compromise in this area & cooling performance is not affected!

 

It will be covered by an IHS.

 

Thanks for this article , help me understand the HBM much more clearly.
Looking forwards to AMD release of these products ,and will be jumping on board as soon as there available .