AMD's Rome is rumored to be designed with 8 Zen2 dies -Can it look like this?

Discussion in 'Frontpage news' started by HWgeek, Sep 22, 2018.

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  1. wavetrex

    wavetrex Master Guru

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    Looks like I was wrong and HWGeek 9 chiplets thing was correct.

    Somehow AMD's engineers were able to solve the latency problem though that center 14nm I/O hub.
    Seems a bit miraculous, but maybe possible by using all kinds of tricks.

    It's possible they went REAAAAALLLY WIIIDE in the connection between core chiplets and I/O hub, similar to HBM works, so (much?) more Infinity Fabric channels than previous gen?


    *Bows down and fades into darkness*
     

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