Discussion in 'Frontpage news' started by Hilbert Hagedoorn, Sep 11, 2019.
It’s really good to see AMD not sitting on there laurels. Lisa is obviously one smart cookie.
I've just put the latest official bios for my B450 and all the interface changed, it looks so much like the 1995 bioses!! They oversimplified everything and don't even allow you to save a frickin OC profile in the bios, just to make room for all these new CPU's. There must be some poor communication between AMD and MSI regarding their bioses.
Anyway I'm guessing that they'll probably ditch some older CPUs info from future newer BIOSs in order to accommodate newer Zen 3.
I'm not entirely sure. Every transistor that switch state consume power.
I assume that if you need to handle 4 threads in a core, that threads has to be able to handle more operation per clock cycle, may them be multiply, add, copy or whatever. That will consume more power and make core larger.
Is 4 threads interesting really?
I'm not sure we'll see 4 thread SMT just yet, as it will have a big impact on caches. Remember L1 and L2 caches are for the core, and shared between each SMT thread.
Doubling up the number of threads effectively halves the available cache for each thread and massively increases cache contention.
For 4 way SMT to make sense you would likely need to see;
1. Micro ops per clock cycle increased from 6 to 8 at least. (Intel are moving from 4 to 5 on Sunny Cove architecture)
2. 50% to 100% more L1 and L2 cache.
IPC on Zen2 is great and already ahead of Intel.
Where they need improvements is;
1. Cache and memory latency
2. Higher clock speeds
3. Power optimisation.
I'd rather see Zen3 focus on those areas to really show what the architecture is capable of.
Who needs frequencies when you have cores... a slight frequency increase would do with 2 more cores for the 6 core line up to 8 and up to 12 for the current 8 core position .. would be killer enough at 4.5Ghz at the same pricepoint and tdp. That would give them a real lead also against intel. Intel can't introduce more cores with HT without excessive TDP now. the 9900K proves that. Increasing cores for AMD would be more beneficial than increasing clocks. And they already said they won't be aiming for excessive higher IPC with the latest refresh. Which I think makes sense.
But that would be my wish. We just have to wait for the end result.
I figure it will basically be a Zen2+ with DDR5 support. That's not insignificant, when you consider Zen2 isn't exactly refined. I get the impression TSMC's 7nm has room for improvement too.
I still am sticking with my original prediction that AM4 will remain with Zen2, where the last products released for the socket are the Zen2-based APUs. That fits in well with their timeline, where Zen3 will likely be AM5.
I'm not sure that's a good idea. Maybe for servers it'd be ok, for home users I think that'll backfire. As far as I'm concerned, SMT works best when all threads within the core are related, since the fetch, decode, and L2 cache are all shared among all threads in a single core. The more threads you add per core, the larger the L2 has to be. The larger the cache, the slower it can read and write data. So by adding more threads to a core, you're basically just trading single-threaded performance pretty much only for highly-parallel workloads, which the average consumer doesn't do.
What I'd really like to see are sets of 2 different cores. One set would be single-threaded cores. These would be very minimal in their architecture, which in theory should allow them to clock much higher. Since they're not sharing any resources, any single-threaded tasks should run very efficiently on these. They'd also be good for heavy multitasking (as in, running many unrelated programs) and most games. The other set would be SMT4 cores. These would be ideal for highly parallel workloads.
Generally speaking, all CPUs would be able to get away with 4x single-threaded cores, regardless of whether you're a hardcore enthusiast or just grandma reading the news. Hardly anyone runs more than 4 highly CPU intensive single-threaded tasks simultaneously. So, the different performance tiers you'd pay for is based on how many SMT4 cores you're getting.
More cores isn't going to make your single-threaded applications run faster. Granted, there are hardly any single-threaded applications that have a need to run any faster than what Intel has been able to provide for the past ~4 years.
As for Intel's issue with adding more cores, it's more a matter of price than TDP. Intel's monolithic design gets exponentially more expensive as you add more cores.
Whait a minute... what about black-jack and hookers?
SMT4? Yeah, maybe with an 80+ stage pipeline, what a shiny future...
They really don't need higher frequency at all. Just another 10% IPC and they would easily match/surpass even the 9900k in single-threaded applications, and that would be true even for the lowest x600 processors, while already having much more cores available, better thermals and less power consumption in the same/comparable price bracket.
Raw frequency only makes sense up to a certain point, which seems to be around the 5ghz realm. Anything above that is either too unstable and/or consumes an insane amount of power, especially when scaling to multiple cores.
I think this chiplet design is still in it's infancy, so I really don't doubt they can make it even better for Zen 3. Another ~10%+ IPC increase is very plausible, IMHO.
yes they do
I have an experience for all of you, sadly a fast internet is a requirement I don't think below 500Mb/s you would see an impact
download a large game (like DOOM 2016) on steam, then downlock to the lowest you can, redownload the same game, you'll see steam download speed is almost 1:1 linked to your cpu clock
and many other things are for sure
Terrible example aside that's got nothing to do with frequency in particular.
As @Ricardo alluded to, CPU performance is a combination of frequency and IPC and it's generally far better to focus on IPC. How much frequency you can achieve is at some level limited by more aspects than IPC, the CPU design matters of course but material and manufacturing limits of the process also makes achieving high frequencies increasingly hard. IPC on the other hand, ie. how much work you can get done per clock cycle, is mainly an artifact of the CPU architecture. Hence a better focus.
P4 vs. the Core architecture is the classical example.
Achieving much higher frequencies at, or below, current transistor sizes may well be beyond reach.
Hmmmm, that is an interesting notion. Similar to ARM's big.LITTLE approach, but more of a single.MULTI (a heterogeneous architecture). Adapting a kernel scheduler to HMP sounds tricky to me, but apparently they've already added support for it in linux.
big.LITTLE is what inspired the idea. And yeah, schedulers will definitely be tricky, but... it's not like Windows does a good job managing the scheduler on current Ryzen chips anyway...
The boost clock stuff like PBO is doing this already and will only get better over the next generations. Personally I dont think its helpful have this approach except if you are very power constrained like say in a laptop or smaller form factor. The reality is AMD needs TSMC to improve their process so they can have have a higher clocked CPU. If you look at stats usually only one core will hit rated boost clocks this will not be a design flaw it will be a immature process issue.
I wasn't saying to take ARM's approach of big.LITTLE. My idea is to have different cores that can handle different types of workloads faster and more efficiently; something that is proficient in both single-threaded and highly parallel workloads, with no compromises.
Don't see that happening any time soon but never say never They would have to make different chips with different architectures like branch predictors with more stages for higher clocks or shorter branch predictors or SMT4 on the slower cores etc. Doing two chip designs is something Intel could fund I doubt AMD would be able to do this as the costs would be very high. However with the new foveros packaging and AMD's chiplet designs they could do it technically speaking as long as windows was fast/slow core aware which I don't have a lot of faith in MS and advanced CPU scheduling. Frankly I think maturing 7nm will yield more bang for the buck for AMD especially if 7nm+ gets them 4.4+ Ghz all core clocks and boosts in the 4.9Ghz range.
I think 5GHz could be a sticky point for Intel and AMD.
Not sure how fast we're going to get beyond it (with normal voltages).
Oh yeah I don't see it happening either, I'm just saying it'd be a good way to maximize diversity of workloads. I actually don't think it'd be all too costly for AMD to do, thanks to their chiplet design. It's basically just one set of cores that are halved of what they currently do, and another set that are doubled-up. So, relatively speaking, the architecture wouldn't be especially complicated.
But yeah, last time AMD did something that sounded good in theory, it heavily backfired. They're not going to take any big risks like this any time soon, and I agree maturing 7nm is a better priority for the time being.
There is just no stopping AMD. It looks like Zen4 (Ryzen 5000) shall come in 2021 on a 5 nm node with an updated Infinity Fabric to support DDR5 RAM and PCIe 5.0.
It shall also include AVX512 extensions, since the BFloat16 instruction set mentioned in the interviews is actually part of the AVX512_BF feature set which requires baseline AVX512 F and VL to function according to current Intel's Architecture extensions programming reference.
I know this is old.....
AMD has multiple chip designs already. They could simply modify the Jaguar architecture to do a big.LITTLE chip. Jaguar actually performs quite well for being a low-power architecture.
In IOT or low power boards for network appliances, Jaguar is doing pretty well.
Pc Engines have their entire boards portfolio based on AMD Jaguar or older models.