AMD Readies Ryzen 5 Series and will offer six- and four-core processors

Kinda disappointing that they went with 2 ccx, but understandable. After all, this way they can convert bad Ryzen 7 chips into Ryzen 5. This absolutely makes sense, since they need money and just throwing away things that can be sold is stupid. Also with pricing of those chips they can have bigger impact on the market and actually force the SW developers to specifically code for Ryzen architecture.

In the end, it will depend on the benchmarks, and especially gaming benchmarks, as these CPUs will hardly be bought for a workstation.

 

The quads are as much as i3s, so even for office work with some skype calls etc in it, they are probably better. Although I believe it's the Ryzen+Vega APUs that will change that game drastically. I can see seriously powerful mini-itx systems replacing a lot of bulk, since the CPUs don't really need a chipset even.

 

AMD trying to remove themselves gradually from the cpu trade? They trying to create the same experience across all cpus concept? Can understand the whole modular concept for ease of scalability. Offering only defective dies for quads when that is the base building block smacks of how serious their cash flow situation is; waste not, want not.

Whole situation reminds me of when it was found out that Oldsmobile engines where used in Chevrolets. Why Olds died out; never recovered. Software cannot cure this. What's the saying, "If you do not know what you are talking about, dazzle them with bull sh|t." That is what this infinity fabric brings to mind. They could not make the cpu work as intended, so...

 

The 3+3 or 2+2 configurations for the future Ryzens don´t seem to bode well for those chips. With fewer cores on a CCX cluster, the cpu is "forced" to use/access the other cluster more times, resulting in a heavy performance penalty because of the latency between clusters... This will surely bring results down more than expected in relation to the R7 parts. And could make gaming performance even worse!...
Looks like the R5 will be good for those who need MT performance but don´t want to buy a R7 because of the higher price and the R3 will sell because they will be very cheap.

Please someone correct me in case i´m saying something stupid.

 

Though I too am disappointed about both CCXs being enabled, there is one optimistic way to look at it:
Fewer cores would involve less communication between the clusters. Though using both clusters will have worse latency than just 1, the latency should still be better than the 8-cores. Fewer cores in general also means less latency between the northbridge, and therefore RAM. It wouldn't surprise me if these CPUs handle RAM frequencies above 3GHz better than the 8-cores.

But here's what I don't get. Imagine the core layout looking something like this:
# - 1 2 - A B - #
# - 3 4 - C D - #
Where 1-4 is one cluster, A-D is the 2nd cluster, and # is the L3 cache. For the quad core models, AMD is basically suggesting the layout could look something like this:
# - 1 2 - A B - #
# - X X - X X - #
Where X are disabled cores. As we all know, cores are often disabled due to imperfect transistors within the core, and compromises its functionality. That being said, we could also expect the layout to look something like this:
# - 1 2 - A X - #
# - X X - C X - #
But here's what I don't get - what happens if all cores in 1-4 are faulty, but A-D are fine? Does that mean AMD is throwing away the entire die? Seems pretty wasteful to me, where I (as well as many others) would rather have a little less L3 cache and no CCX.

 

Maybe you´re right but i think the cores configurations in the R5/3 will bring performance down more than it should in regard to the R7 parts. I understand AMDs´s decision about this questions because financially this makes more sense.

About your last question, maybe we could see an Athlon/Sempron in the future with an entire cluster and only 8mb of L3 cache for the Athlon and no L3 cache for the Sempron??? Attention, this is a (very) wild guess!...

 

I don't understand why it would worsen performance over the 7 series. The CPU's microcode would account for the fact the extra cores are missing, so if anything it should reduce latency because there are less cores to communicate to.

Think of it like an office meeting around a table with 8 seats, where a couple seats are vacant. Though the overall objective would slow down (because the people missing have to be told in another session what to do), the meeting itself would be quicker because there are less people to account for at the time; more people means more time is spent making sure everyone is on the same page.

If you really wanted to take the meeting analogy to the next level, each side of the table are different departments of the same company.

 

Being the fact that the it 7600k is 3.8Ghz/4.2Ghz boost, it's already got a frequency advantage and we already know the IPC of the latest intel processors should be better then AMDs

But IF everything was equal, Mhz, IPC, and the only difference was 2 cores and SMT, the 2 cores would equal to the 50%, and the SMT would likely be 5%-25%, and that 19% falls right in line.

Again, that would be IF everything was equal other then the cores and SMT, but it isn't, so 69% when it's at a disadvantage in everything but cores and SMT, sounds really good.

 

Well let´s look at the R5 with 6 cores, 3 in each cluster. Imagine a task that uses up to 3 cores, the cpu will perform normally because each cluster has 3 cores. Now the same task uses 4 cores, this will lead the cpu to access the other cluster more times than it would if the first cluster had 4 cores, resulting in higher performance penalties because of the high latency of using the other cluster. This is gonna be even worse for the R3 parts (2+2) because it will need to use the other cluster even more times.

This is my idea of why the R5/R3 will perform worse than they should but i could be completly wrong so feel free to correct me.

P.S. I hope i phrased my idea correctly...

 

Intels higher cores work the same as intels lower cores at the same frequency, i think what is being said here is that if AMD did it differently and didn't have to deal with the latency issues on their lower core CPUs, that would mean a 3.4Ghz 4-core would beat out a 3.4Ghz 8-core in some games/products, which is what i believe is being implied that AMD would not want to do.

lol "real cores", that's a good one. A term that people seem to have no idea what actually means, and realistically stems from them just not "liking" the way "real cores" are put together.

Your statement doesn't make sense

If you want the fastest CPU, that'll be either the Ryzen 7 1800x, or the i7 6950x

Both processors will go back and forth on who beats who from most power

So, since they are fairly even and go back and forth the question becomes, do you want to pay $500, or $1700 for fairly similar processors?

 

Ah, you make an interesting point there - I hadn't thought of it that way. But, I wouldn't say I'm all that concerned about it. Consider the following:
* To my knowledge, the only reason for the clusters to communicate to each other is because of the L3 cache. Otherwise, each core operates independently.
* We don't yet know how much L3 cache the quad cores have, but the 6-cores still have 16MB, just like the 8-cores. That's a lot of extra cache.
* From what I recall, there are 2 chunks of L3 cache, one on each side of the CPU. Communication between each cluster is likely necessary if one cache fills up too much.
* But, fewer threads means less L3 cache is needed, so the L3s may never fill up enough. The L3 should be overkill for these lower-end models.
* I'm sure the CPU is designed so each L3 cache prioritizes data necessary for the cores they're neighboring. In other words, the L3 cache "on the left half" likely won't store data for cores "on the right half", though obviously there'd be exceptions to that rule.
All that being said, there might not really be a need for CCX to transfer data across the clusters if each L3 has a surplus of storage for it's neighboring cluster.

I may be wrong - I haven't looked much into how CCX works but the way I see it, the only 2 things that really separate these Ryzen CPUs from dual-socket setups (in a functionality perspective) are the shared L3 cache between all cores, and, you don't get the extra memory channels of having 2x CPUs. I'm not sure how crippled dual-socket boards are due to latency, but it can't be that bad since they're still being made.

 

Because keeping the extra 8MB of L3 is faster than not splitting.

 

Only for very specific applications. I'd definitely like to have the more cores, but not if that means a compromise with lower single thread performance!

So you can probably understand why I'm completely disappointed in these ryzen cpus - even the ones supposed to rival intels gaming cpus fail to beat them.
Not to mention all the memory issues and bad design with split CCX's.

Yes, there aren't any benchmarks yet, but we can see the low numbers in the OP and we know from the 8 core ones that they'll overclock like a dog.

 

I hope they came to that conclusion by checking game performance as well, not only video encoding and rendering.

 

Herp. I read it and thought it sounded stupid. But didn't care enough to edit. Ofc I know core is a core. But oh well

 

It also allows them to use two defective CCXs for a CPU. The other configuration would have required a "clean" CCX for a quad.

 

Well my thoughts for this are:

* I bet the extra cache is faster or they know the latency issue can be addressed via software. If not, we should have a 1450 with a single CCX priced slightly higher as a gamer CPU.

* I would expect an R5 1475X as a single, binned CCX @4.1 for gaming in the next months. We are mostly gamers here but the market share AMD wants is on the workstation/oem and server side.

A single CCX Ryzen APU looks extremely attractive for laptops

 

A single CCX should be around 100mm² max, the 4096 core Vega is around 540mm², so a theoretical configuration of a quad Ryzen with a 1500+ shader Vega could be on the ~270mm² mark.

That would be a great laptop chip at an affordable price.

 

Unless AMD plans big surprise, we are getting Ryzen APU: 4C/8T + 12NCU (768 SP)
But even that may be interesting if NCU clock well as AMD promises clock bump.