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AMD NAVI Radeon 5700 Product Announcement thread

Discussion in 'Frontpage news' started by Hilbert Hagedoorn, Jun 10, 2019.

  1. Fox2232

    Fox2232 Ancient Guru

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    GPU chiplets are in pipeline. GPU itself is embedded in infinity fabric already since Vega. For certain tasks Chiplets are no problem. For other tasks, access speed to memory attached to other GPU chiplet(s) may prove to be an issue.
    Using I/O hub as with Zen2 may prove to be problematic as GPUs use magnitude higher bandwidth than CPUs. Complexity may prove to be too much.
    We'll see with 8-channel 8chiplet Zen2. But that uses rather big I/O die and that has to be paid too.

    It may start to be useful in case AMD goes for 5 times 10 Dual-CU (20 CUs per chiplet = 1280SP in 1st Navi configuration) => 6400SP.
    But monolithic GPU with 5120SP may still have reasonable size (price) on 7nm to offset cost of interposer for chiplets and huge I/O die.
     
    Aura89 likes this.
  2. Loophole35

    Loophole35 Ancient Guru

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    @Fox2232 do you know if RDNA has a CU limit like GCN did?
     
  3. Fox2232

    Fox2232 Ancient Guru

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    It should not. I think that it is reason why RDNA on macro building level looks like it is GCN partly turned inside out. But I can't remember it being written on any slide or supporting text.

    64CU limit was end of the road for AMD since Fiji. Since that point AMD could only go for clock and beefed up CUs. Doing that again would be end of their GPU division and claims that they are going to deliver/compete with enthusiast GPUs again would be false.
    (Or rather those GPUs would be limited to mainstream performance for some time and then to entry level.)

    They may have one of following approaches:
    - Current Shader Engine has 10x Dual-CU (1280SP)
    - > This can be either duplicated (more Shader Engines) or count of Dual-CUs per SE may go up
    - > Duplicating entire SE may have some issues with access to parts that are needed but are in center of GPU (ACEs, Geometry Processor, ...), but that's just speculation on my side as bandwidth required may be actually pretty small
    - Each SE caries rasterization and L1, those can be beefed in case more CUs are used per SE too

    I honestly think that every weakness I may come with may prove to be overcome just by Infinity Fabric on which AMD made big bet and it seems to pay off in CPUs.
     

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