AMD Confirms Development of Consumer CPUs with Hybrid Architecture

The issue with big / little architectures always was, is, and will be core parking and too aggressive power savings. THAT's why I don't want it, because I can already see that they will need multiple microcode / scheduler / bios updates until it works. And honestly, for the prices we pay, that's even worse, we're supposed to just use the hardware we buy.

 

One engine for high speed and one engine for low speed, best fuel efficiency and lowest cost of ownership, hell yeah

 

IDK man, i just want as much cores as i can pay and two or four cores turboing as much as the architecture can, right now I'm running two old Xeons and they beat to the hell any pc i use, i just want big computing power, i don't care if i spend a little more in electricity and i don't need a thin laptop to sit down in Starbucks mimicking I'm working.

 

Exactly. 7600x should have them already when 13600k has 8.

 

Prius "engine" and "high speed" in the same sentence???

I drove a Prius once - out of necessity - but with a paper bag on my head because I didn't want people to recognize me: ugly car with no soul, no personality, no fun - like these big/little cpu's.

I don't know what's wrong with AMD: first they are copying Nvidia with their marketing/prices policy, etc., now they are going Intel road which I frankly thought to be a dead end and at some point Intel will come to their senses and go back - I want a desktop PC not a giant smartphone - enough already that I have Microsoft with their operating systems that are starting to look more and more like the mobile UI for smartphones...

 

I suppose you haven't seen the 2023 Prius? Now that EVs have proven they can be sporty and efficient, seems Toyota recognized they need to rebrand the Prius as something that isn't just for tree-huggers.
In any case, there are high-speed hybrids out there. While many of the slowest cars of a generation are hybrids, some of the fastest are hybrids too. There is no reason why a hybrid CPU couldn't be crazy powerful, but, it would imply the smaller cores aren't built to sip power. Think of it like this:
You have a CPU with 8 big cores and 8 small cores. The big cores have more cache, advanced instructions, SMT, etc, but the small cores have crazy factory clock speeds like 7GHz. Depending on your workload, the small cores could end up being the faster ones.
But even if that's now how it's done, like I said before: so long as the E-cores aren't replacing P-cores, it's just free performance. I would gladly take 4 E-cores over the waste-of-silicon that an iGPU will most likely be.

 

As far as I know, Intel came up with E-cores because it couldn't do any better (in a short time) to compete against AMD on core count and multicore performance . There is no need for big/little in desktop, you just reduce clock speed, voltage etc, if needed.
But my only real reason to dislike it is backwards compatibility (a good one) with old OSs.

 

There is always room for improvement, hybrid design allow them to hit more of their targets, I think its worth noting that amd's take on Efficiency cores , is not likely to be that similar to intel's, I don't think you'll see the same level of asymmetry, seems more like they need a way to pack more cores into a smaller space without increasing tdp, and big cores , while great for single threaded applications, hog die space, so if amd were to couple a "large core" ccx, with a cache reduced and size optimized core ccx, that would get them basically all of the benefits they are missing out on without as much scheduling hell, I think that what we will basically see is zen4/5 x3d coupled with zen4/5c,

 

Or in this case, two clowns.

 

It took Intel a while to iron out any bugs and issues, and even a new gen to improve on it. Imagine how long it will take with AMD.

 

Exactly my thinking. And as there's already slang terms for it (the aggressive parking I mean) I can imagine this ending up in a troublesome first generation.

 

Hopefully AMD will learn a little bit from Intel's learning.

 

most of space used on modern CPUs is used by Cache mainly and secondary by what was called northbridge years ago. having some cores (maybe one package) reaching higher frequency than other is fine, it's not so far by current BIOS capabilities, however changing instructions supports creates a lot of issues outside embedded environment.

 

Must be the only one who finds this exciting. The issue with Intel is the manufacturing process, nothing else really. The approach they took, they had to take earlier because they hit thermal limits before everyone else, because of said process.

It was also obvious from the mobile space for a loooong time. The desktop just hit its own thermal/power limits later.

 

amd solved that problem essentially, in the case of avx 512, zen 4 doesnt support 512 bit simd natively, instead 1 512 bit op is run as 2 256bit ops, so if amd wanted to say go native 512 bit simd for the big cores and stay 256bit for the low small cores like intel , they can do that without any difference in the instruction set.
since were talking amd , north bridge is the basically the io die, and ccds the cores, so if amd wanted to put a big core chiplet with a small core chiplet, that would get them the hybrid architecture without much work, infact all amd dual ccd ryzen chips already sort of work in a hybrid manner, with 1 ccd being a high quality bin and the other a low quality bin, and they use cppc prefered cores to manipulate the windows scheduler to keep high priority lightly threaded workloads on the high frequency binned ccd. this is alot simpler than what intel does, but it does work pretty well, and it would mostly work 'out of the box' if amd were to launch a zen4+zen4c part today, (which would presumably be 24 cores.)

 

the 2*256 trick was mainly for scalability on software and frequency issues. Going native 512-simd bits isn't so smart if this impacts on frequency and lower capabilities of 256 and 128 simd pipelines. Looking how good this scales, this was the right choice and probably will be for a lot of years.
The problem is, outside cache, the only thing you can cut out from a cpu core to make a low power version is removing simd and other instruction set to shrink the ALUs of integer and floating points and this on PC is really bad. Making a smaller CCD with less cores may also work, not so much different from what they are already doing. But even if they do all this in the right way, without cutting ISA capabilities in a low power cor set, the issue now moves on software side: OS schedulers don't make miracles with software not aware of this architecture differences, especially if are software that try to spread the threads upon multiple cores manually (that is the right way to do for low-latency and high performance multithreading in multiple scenarios). For sure, if the OS scheduler moves its useless background tasks on the low power core package, this may probably be the minor pain.. but borderline scenarios will always face and hit this changes. If they wanna avoid all those issues they should simply don't do it outside laptop CPUs.

 

As long as there's a 8 P cores 16 P Threads chip for gaming then who cares if they slap a few E cores into the mix too.

I don't personally like it because it means more bloat as it'll need special software to run and add a lot of complexities for no real reason.

If it's for lower end stuff then that's ok for power saving and the like but why does a gaming chip need E cores when it could be 95w for a good 8/16 cpu.

It'll be handy i suppose for laptops that could use E cores while on battery only.

 

since its all decoded into micro and macro-ops, you can support a full instruction set and not have full dedicated hw, the cache is not the only thing that they can cut, if that was true, the e cores in alderlake would not produce greater performance per mm^2, for reference , 4 of intel's ecores, are roughly equivalent size wise to 1 intel P-core, and together offer greater performance, avx 512 or not, performance does not scale linearly with transistor count, because you run into bottlenecks as it gets bigger.
also amd's avx-512 implementation , is actually alot smarter than you think, it reduces power consumption and improves utilization of the simd units, its quite the contrast to zen 1 and bulldozer, which do something similar .

The concerns about the scheduling are overblown imo, every android phone in recent times uses big.LITTLE, and they don't really have scheduling problems, the actual problem is windows and intel making things overly complicated when they don't have to be.
For instance the linux kernel , still does not fully support the thread director yet, and aside from issues at launch, there are basically no performance problems now. scheduling works as expected.

 

I wonder if the little zen cores would be just zen cores with halved cache or something! Soo if the analogy was with zen 3 would be like 8ryzen 5700x cores +8ryzen 5700g cores ... Totaling to 16 cores