AMD Big Navi would see two product versions with different GDDR6 sizes (12- and 16 GB)

Discussion in 'Frontpage news' started by Hilbert Hagedoorn, Aug 8, 2020.

  1. PrMinisterGR

    PrMinisterGR Ancient Guru

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    Or have a super fast I/O subsystem thus not really caring about this. But this is console heresy and it's not taken well in these forums :p
     
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  2. deksman2

    deksman2 Member

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    Actually, the manuf. process which AMD will use for RDNA 2 was stated to be N7P (non EUV).
    That node only allows 10% higher efficiency or up to 7% higher performance (one or the other).

    As for the rest...
    Well, AMD created 'enhanced Vega' for Renoir for which they managed to get a total of about 56% higher performance per core.
    Putting that into context, only about 15% of that performance gain came from clock increases (which went up by about 30%).
    Performance never scales linearly with clock increases.
    About remaining 40% of those performance enhancements came from uArch improvements - some of which AMD said they will use in RDNA 2.

    Contrary to what you think, power consumption goes up EXPONENTIALLY with clock increases.
    I don't 'ignore' anything... AMD has a history of not optimizing voltages on their GPU's in order to increase the number of functional dies...
    If they do optimize the voltages, all the better... I was giving conservative estimates for worst case scenario.

    And you completely missed my point.
    40CU's would be 50% higher performance than 5700XT at SAME power consumption (225w)
    N7P node allows 10% higher efficiency resulting in that power consumption to go down to 202.5W
    If you drop frequencies by 20% (which drops performance by 10% and power consumption by roughly 40%), you arrive at about 121W TDP at 40% higher performance than 5700XT.

    Scaling up from there with more CU's (depending on how much AMD adds), increases both clocks and power consumption.

    Now, CU's apparently don't add as much to power consumption as do frequency increases... but they DO add something (about 5%)... whereas clock increases result in exponential increase in power.
    So, bearing that in mind, my power and performance estimates would result in a rough ballpark (and ironically enough, certain rumors which were released to now agree with those estimates).

    Of course, I keep an open mind to the possibility I am horribly wrong... it was just a late night musing of mine, nothing else.

    IPC increase usually means you can get X % of performance at same frequencies (without increasing power consumption). That further depends on how the uArch is designed and modified to work on a given manuf. process and at which voltages.

    Of course nothing is for free. I took that into account.
     
    Last edited: Aug 12, 2020
  3. Fox2232

    Fox2232 Ancient Guru

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    Please, not again. What alternative reality are you living in?
    APUs from 3000 series had max GPU clock 1.4GHz. APUs from 4000 series have max GPU clock 2.1 GHz. That's 50% right there.
    No, it does not. increasing clock does not magically increase charge each electrical element in CPU holds. That's why it increases in linear fashion. Once you increase Voltage to get that higher clock stable, you increase charge required per FLOP. Multiplying the two will get you exponential power draw. (Simple physics.)
    Your conservative scenario meant 2.6 times jump in performance per Watt!!!
    They will not. To get 50% more performance per CU, you either need appropriately higher clock. (Don't even dare to begin expect 2.8GHz GPUs) Or 50% more SIMDs per CU. While AMD has patent that shows variable SIMD count and type per CU, all currently known rumors state same 64SIMDs per CU as RDNA1.
    You have never done that, right? 20% GPU downclock will result in some 18% performance loss unless you started with GPU that was severely bandwidth starved by memory. And no, 20% downclock on Navi does not even reduces power draw by 30% because AMD did not go that last mile that is very energy inefficient. It would be true if AMD sold those GPUs as 2050MHz ones at higher TDP.
    Feel free to scale from totally wrong assumptions.
    5% per what exactly? Per one CU? Per 100?
    You are horribly wrong. And no, you did not keep open mind, otherwise something would sink in from all those who explained you all your errors.
    No, again! It is about FLOPing. If increased IPC comes with more FLOPing transistors to deliver more results per cycle, it eats more energy. And IPC never had anything to do with manufacturing process. If you take iP3 and build it on 7nm, it will have exactly same IPC as iP3 built at 180nm. At 1GHz, they'll have exactly same computational output rate paired with same memories.
    Sorry, but you did not. It is economy. And what you expect is expensive to make while it leaves performance on table and will not even fit 300W TDP because you horribly misunderstood official statements, even crazy rumors and multiplied anything and everything till you got completely out of picture.

    Maybe you should google nVidia's GPU performance improvements over last decade together with power efficiencies delivered by foundries. And then see how much from each generation jump was due to ability to make bigger GPU at higher clock thanks to foundry. And how much from it was actual "IPC" improvement in architecture.
    AMD was not in any better place. Their 1st really good jump was from RDNA1. But they are beefing CUs, that means transistors which are dedicated for DX-R and not traditional rendering. Bigger CUs means smaller budget for more CUs as they are more expensive.

    But I doubt that you'll learn from single sentence I wrote.
     
  4. bobblunderton

    bobblunderton Master Guru

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    I have x570 here, I can't wait until they decide to actually make more industry-wide use of PCI-E 4.0.
    Generally speaking though, until everyone can exceed VRAM (like those on PCI-E 4.0* and still have somewhat playable FPS), I can't design for over 8gb of VRAM sadly.
    I sure wish I could, 1/8th mile of semi-realistic tunnel can take 500gb just for the model.
    Doing a real life quality 6' (a little over 2 meter) long hanging vine can take 100mb in itself, again, just for the model.
    *Not saying that pci-e 4.0 is a veritable get-out-of-VRAM-limit free card, but it could help a bit until model detail/texture size catches up.
     

  5. PrMinisterGR

    PrMinisterGR Ancient Guru

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    VRAM is and will always be necessary. The great thing would be if we there was transparent compression on all sides of the "transaction" here. Compressed SSD storage, compressed RAM, compressed VRAM. This would give exponential bandwidth increases, and if it was done in hardware (as it should), for zero cost. I can't believe I'm saying this but PC as an architecture needs this step.
    I find it incredibly stupid when people were disparaging AMD for implementing PCIe4.0, and I find it the same when they disparage the system design of the new consoles.
     

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