Alder Lake DDR5 Performance Benchmarks Leaks As Well

Discussion in 'Frontpage news' started by Hilbert Hagedoorn, Sep 13, 2021.

  1. Hilbert Hagedoorn

    Hilbert Hagedoorn Don Vito Corleone Staff Member

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  2. Horus-Anhur

    Horus-Anhur Master Guru

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    Big numbers for memory bandwidth. But also for latency.
    On a CPU, usually, latency is much more important than bandwidth.
     
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  3. Mda400

    Mda400 Master Guru

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    Wonder what it would be like with 1T command rate.
     
  4. David Lake

    David Lake Master Guru

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    Very unstable :p
     
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  5. Horus-Anhur

    Horus-Anhur Master Guru

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    Probably it could reduce latency by a few ns. But not much. Maybe 2-4ns.
    Just guessing since command rate doesn't have that big impact in memory latency.

    But there's one thing to consider.
    Those timings are very lose.
    Cl40 @ 6400 means an absolute latency of 12.5 ns.
    For comparison, CL16 @ 3800 gives an absolute latency of 8.4 ns
    For that kit of 6400 to reach that value, it would need to have a CAS of 27.
    But this is only one timming. And not even the most important.
     
  6. Ssateneth

    Ssateneth Member Guru

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    Thats not fair. You are comparing JEDEC to XMP. Compare JEDEC to JEDEC please with no overclock. Also, this aida is old (build 5600, most recent is 5700). An even newer build will probably come out to fix certain issues with the benchmark,
     
  7. waltc3

    waltc3 Maha Guru

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    And so....when's it going to ship? That's the question for Intel atm.
     
  8. tty8k

    tty8k Master Guru

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    785 CPUz score for a 4.6GHz 12600k ES
    Looks alright.
     
  9. JamesSneed

    JamesSneed Maha Guru

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    To be fair we need to compare whatever can be bought reasonably priced and will run on ADL vs similar price points for DDR4. Using XMP profiles is fair game. JEDEC to JEDEC will make DDR5 look better than real use cases with XMP especially since they stopped at 3200Mt/s for DDR4.
     
  10. Dazz

    Dazz Master Guru

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    CPU Z records the lowest frequency, so i suspect it is recording 4.6Ghz on the little cores while the big cores will be running at 5.3Ghz when doing the single-threaded test and 5Ghz all large core frequency.
     

  11. P.O.N.

    P.O.N. Active Member

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    Impressive numbers, latency included. Could ECC have something to do with that?
     
  12. kanenas

    kanenas Master Guru

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  13. Horus-Anhur

    Horus-Anhur Master Guru

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    I don't think so.
    DDR5 ECC is not what we usually think about ECC.

    What we know as ECC, is end to end verification. To make sure the bits are the same, when transferred from memory to CPU.
    This tries to detect bit flips, when moving data out of memory. And correct them.
    Because this is an end to end ECC, there is a latency cost.

    The ECC that is now standard in DDR5 is only on chip.
    Because memory cells are becoming smaller and chips more dense, this can cause more bit flips, inside the memory chip.
    In this case DDR5 ECC tries to detect and correct bit flips, only inside the chip.
    But because this one is done only at the memory, it might not have any additional latency. Or if it does, it will be very small.
    This also means that it's possible to use lower quality memory chips that usually would have too many bit flips. So it increases yields for DDR5.
     
    Last edited: Sep 14, 2021
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  14. nosirrahx

    nosirrahx Master Guru

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    I know for SODIMM the fastest DDR4 with JEDEC timing is dual rank DDR4 3200 CL20, not sure about desktop RAM though.

    https://www.kingston.com/dataSheets/HX432S20IBK2_32.pdf
     
  15. tty8k

    tty8k Master Guru

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    The small cores run at 3.4GHz all or 3.6GHz single so it's not that.
    The big ones run at 4.9GHz single and 4.5GHz all.

    Given this is an ES I'd suspect that is single core boost on a big core.
     

  16. user1

    user1 Ancient Guru

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    It might be running at effectively 4t if geardown mode is enabled, in which case it would hit latency pretty badly, It wouldn't be surprising since this would be intel's first memory controller at such high frequencies. not like 10nm is going give intel some free frequency gains this time around.
     
  17. brogadget

    brogadget Active Member

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    bench screen of my current x299 system (quad-ch.), just for comparison:

    AIDA_cachmem.jpg
     
  18. Horus-Anhur

    Horus-Anhur Master Guru

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    I didn't have Intel CPUs, for the last 4 years, so I don't know exactly how settings affect latency.
    But I'm guessing that if we tight those timmings, we might see latency go down to the 50s range.

    But with the first bios and DDR5 memory ICs, it won't be as low as DDR4 is today.
    It might take a couple of years for the tech to mature.
     
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  19. Undying

    Undying Ancient Guru

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    When haswell-e 5820k lauched as a first ddr4 platform it didnt take years to mature but comfortably beating any ddr3 platform right away. Despite higher latency it had much higher bandwitdh and many architectural improvements over older systems.
     
  20. Horus-Anhur

    Horus-Anhur Master Guru

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    I was only talking about latency.
    Of course, Alder Lake will have better performance overall, than previous gens.
     

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