Intel Cascade Lake AP: 48 cores with 12-channel DDR4 in multi-chip package

In jest of Intel's borderline slander of AMD in some of their investor slides a few months back.
If someone would be so kind as to link the slidedeck, that would be fantastic. Phoneposting from work right now so hunting it down would be difficult for me.

 

is how Linpack should be run, and how AMD recommends it
Intel's HT is disabled as well

https://newsroom.intel.com/wp-conte...cade-lake-advanced-performance-press-deck.pdf

http://www.crc.nd.edu/~rich/CRC_EPY...18/Installing and running HPL on AMD EPYC.pdf

 

oh i know
it's people repeating that slander that bothers me.
it's like calling Moore a tinkerer.

 

Intel said AMD is using DESKTOP cpus glued together on servers, that's the issue.

 

All the lil AMD fans have to post......like we owe them!

 

Hold on your boobs, cause Zen2 surely gonna take 'em away

 

Not as long as Spectre vulnerabilities

 

Because that's how you compare (get to) "Instructions Per Cycle", guess what, that stands for.
But you was probably thinking "Instructions per Core" which is now intel's way to call it. Think about it for a while. Anyone who understands "information" laughs to this imbecility intel called it. It does not have unit of measurement allowing it to have any relevance at all. What is that? Instructions which fit into L1 cache of Core at any given moment? They simply created abbreviation which they want to use for people to forget about IPC since AMD did catch up to them.

At time of Bulldozer, intel could come and say: "Hey, we have double IPC. And therefore out 4-core 3,7GHz chip wipes floor with AMD's 8-core clocked at 4,8GHz in almost any workload."

But today's Zen IPC tell's simple story. Intel's last fortress of defense is superior manufacturing process allowing them to clock higher.
= = = =

And one can learn from nVidia something. Lower Power consumption => Lower vDrop => higher transistor stability in terms of not falling into uncertainty area between 0/1 => higher clock. (Wait, down-volting 300W Fiji/Vega shows same thing.)

 

That's what the meaning of IPC of CPU. Sad that you don't know the same

 

Hard to resist laugh on this slide now



LOOOL xD

 

And they are wrong, its other way around, AMD used 4 part MCM design for server CPU and using lower quality parts with disabled stuff for desktop. Intel will need to go same way if they want to survive and actually there is very little difference between Desktop and Xeon CPUs on Intel side, they just have more money to make more chip variants based on number of cores, but it does not matter for future.

What AMD presented for Zen2 is what actually everyone will follow in future and is probably best option around and any custom SOC based on this architecture would require near zero cost and time to prepare. They could probably even slam Arm core next to x86 if that's needed.

Also for bug fixes and changes that usually require whole chip redesign you could manage by updating just one chiplet which would be much cheaper and faster.

 

https://i.**********/05S7vtVf/CPU-IPC-GURU3-D.png