G.SKILL are thrilled to release new ultra-low latency, high-speed DDR5-6600 CL34 32GB (2x16GB) memory kit for the latest 12th Gen Intel core processor and Z690 platform.... G.SKILL Announces New Ultra Low-Latency DDR5-6600 CL34 Memory Kit
Does first timing matter so much that other timings can be so loose? Memory overclock is still a myth to me, and I tried to do it a lot of times.
What about DDR5-10000 with CL 500? I know that this CL34 its probably good, but i think that all these lighting speeds with high CL are just bait for people with not enough knowledge..
The latency timings are in clock cycles so you can divide the CL/CAS (Column Address Strobe) by the frequency to get a relative comparison, 6600MHz CL 34 would have the same Column Address Strobe time as 3300MHz CL17 for example. The silicon might switch faster allowing for higher clock frequencies but it still takes about the same amount of time for the tiny capacitors that hold the bit values to be charged and discharged.
A pretty complicated question. RAS selects a row and CAS (CL) selects a cell in the row (a column). That's how memory is read. When you think about it in a way of selecting a row (RAS) and then reading the cells (CAS) in that selected row, it would seem like CAS is more burdened. However, I don't think it's quite that simple. The CPU doesn't actually directly control the memory chip anymore, like it probably did still in the 70's, but instead DDR has its own logic and buffers. When you are accessing memory totally randomly, tighter timings become more relevant, I reckon, because modern memory system always tries to guess what you need next to speed things up. Maybe someone much wiser will give you a much wiser answer.
Imagine zen4 and raptor lake cpus with such a high ram frequency, it will smoke everything we have today.
All the timings matter. I thought the same thing, that timings didnt mean much it was all about speed. Then i got my 11900k and started really trying to OC my 4000mhz dims. getting to 4266 at 17-17-17-32 and then really tightening up the subtimings and now have my mem latency around 47ns. It just really is crazy, how much more responsive your mouse is in a game, or even just the the game in general. I thought 240hz was smooth the way it was. Then got this system fine tuned and almost got motion sickness from the fluidness, which is weird cause i dont get motion sickness ever.
the high cl is ok so long as the platform is equipped to deal with it, ddr5's design a bit of a tradeoff , sacrificing latency for higher bandwidth and lower power consumption, this tradeoff is being compensated for by having big caches on the cpu, you can pretty well reduce the impact of the higher latency to zero alderlake doesnt really benefit much from the use of ddr5, it will probably be zen4 or whatever intel cpu that comes after the refresh , that can actually gain something from it. different story in server land however, much of it is i/o limited, so the extra bandwidth helps alot.
Well yeah compression especially big files is a sequence read/write ordeal mostly so cl gets a secondary role and bandwidth is king !
Really wish its the last few batch of DDR5 so it wil be over 10kmhz then it a good buy rather than keep changing.
