And that's a lot. In Geekbench some scores leaked, and while we don't trust geekbench scores, the specs however are listed in great detail. ... AMD Zen 4 Based Genoa CPUs Get 1 MB L2 Cache per Core
Sounds like it will kick ass! Of course it absolutely needs to, considering Intel is back in competition.
this is cementing AMD's status in Enterprise and i'm sorry for Intel as they aren't going to get any traction outside of legacy customers with less intensive needs. software defined feature sets will not cut it against this.
This would confirm AM5 1MB L2 per core also right? As far as I know cache is not something that previously has had yield problems, so there should not be any leftover desktop chips with half the cache blocked off, unless they are made on a different production line.
It's kind of funny seeing how 1MB of L2 is considered large again. I had an old Opteron 180 (socket 939) with 1MB of L2 cache per core. Granted, it didn't have an L3 and only 2 cores.
excellent point. point of interest is that both Genoa and Ryzen have an spankin' new fab for limited models, and both Genoa and Ryzen (and TR) share fab runs on existing fabs. the 3D cache models are at maximum output (wafers per month) but only one fab so the lion's share is the Genoa 3D cache and the consumer halo is the 5800X3D, actual numbers of 5800X3D are the just to make the point. which is also why you might expect the price of the 5800X3D, while the Genoa prices are "a steal". the main fabs in use have spent the last year pumping out iPhone 13's so volume production is no issue with nothing like 3D cache needing to be dealt with. AMD has been takin' the cache train for a bit and i don't expect (but don't really know) them to be doing cut-downs there
You would want to compare that L2 to todays L2+L3 to be fair for a size comparison. Back in the day that was a pretty large L2 outside of some of the big iron like Sparc or Power chips.
Yeah as long as AMD is keeping the chiplet designs the same which I have heard no reason why they wouldn't. Doubling the L2 is going to help with latency with the larger L3 caches since they have a little more latency so going there less often should help performance.
Athlon Xp Barton introduced the 512KB L2 cache if i recall correctly, which also killed the P4's frequency lead. Athlon 64 FX introduced 1MB L2 but also costed 1k euros...so idk if that was mainstream. But those were in a time that L2 was the last level of cache( also process nodes were influencing cache latencies) L2 size depends on latency penalty, ever since L3 cache became mainstream Now L3 is the one that gets regular changes and its latency is not the most important metric, as we see with Zen
What I really want to know is what are the planned 3D cache layouts for Zen 4! It is really between ADL, 5800X3D or Zen4 for gamers who want top performance now!
could be mix, There are 2 zen4 variants, genoa and bergamo, bergamo cuts some cache to pack in more cores, both could be used on am5.
assuming amd is using chiplets for bergamo, Its possible that they will be used for some products on am5. if they are to use them, it would likely be for lower end parts. Nothing is ever set in stone with this sort of thing.
tru dat however i do know the production schedules and the fab sites which doesn't mean you're wrong, it means i'm using deduction from the wafer allocation. what is very telling to me is the brand new fab in Kaohsiung (3D Cache) they are producing Genoa w/3D cache AND 5800X3d/Zen4 3D as the only products throughout this year being made there. that kind of exclusivity is rare and expensive (typically enjoyed by Apple and AMD in past with ryzen 2). in my way of thinking, that's close to a lead pipe cinch. however, given that lithograph masks are highly transportable (even though they're not typically moved from site) that doesn't guarantee me from having anything more than a hunch
fair enough, my line of thinking was that since bergamo is for higher core counts, the actual number of skus that would utilize bergamo silicon, would be only for >96 cores most likely(since genoa fills the market below), which would mean that the opportunity for binning is limited, however how much that matters of course depends on allocation as you say.
yeah, and as a tech nerd i highly appreciate your going with moar cores as a first reaction but in the marketplace that leaves the cloud and cloud virtualization for all of those damn cores the services being sold today are bonkers - why pay for VM software when the lightest weight laptop (metaphorically more than literally) now can have as many VMs running as the need dictates and far more than your traditional workstation/desktop. or running CRISPR etc... AMD was far more visionary than i ever expected at the time, and i was thinking i was bordering science fiction.
