AMD Ryzen 9 16-cores CB15 4346 Benchmark?

1.5 v

 

That's an extremely high core voltage even for 12nm node

 

Guys, first check stepping please!
This is an A0 CPU.
Supposedly very first stepping of engineering sample.

 

It wont differ that much or at all from a retail one.

 

I do believe the vcore will drop a bit on the final stepping otherwise this is going to be called a kettle or immersion water heater

 

Where all the power is going? Pay attention to max 5.5W per SMU=~88W for 16C, while the Package max is 245W.
On 2700X each SMU was ~14W=112W total core/130W Package.

 

Isn't the L3 too low for a 16/32 CPU? The 3900x 12/24 has 70 mb L3.

 

My thought as well...working in the 2x larger cache with all of those cores may well be the hold up. I'm sure they will lick it soon.

 

"so please do take these screenshots with some disclaimers as that CB screenshot also says Windows 8"

cinebench R15 ALWAYS says windows 8, on any windows 8/10 version..

-andy-

 

everyone jumping to conclusions based on a shot from an early engineering sample.

 

It's right, Zen2 L3 cache for 6/8 cores is 32 MB and 64 MB in 12/"16".

L2 cache is ok too, 8 MB in total.

The OC feels hardcore at VCore...

I'd like to know more about new chips' specs...

 

1.57V for a previous gen 2700 would be death. 1.5V would be rapid degradation, like in weeks. I get nervous when the LLC/automated controls of my motherboard sometimes allow for the voltage to spike to 1.47 under constantly 100% loads.

 

It's Almost like those with samples need to push the limits to design their products around big fat 16 core under extreme conditions and voltages

 

Yes they are.

you can disable 1 or 3 cores per ccx instead of 2.

 

This is an A0 CPU which likely didn't clock up very well and is likely missing a few tweaks. Im sure not only did AMD make tweaks but so did TSMC to the process since this was there first high frequency CPU on 7nm. This CPU could be back from november of 2018 so who knows how jacked up things were initially on scaling up frequency. I just tend to ignore things like this because its worst case scenario on early engineering samples.

 

It doesn't? 70 MB is total cache, i.e. 64MB L3 + 12 * 0.5 L2 = 70 MB. It checks out. This one would have 72 MB.

 

Thank you for showing you don't know what you're talking about. Seems you are doing a lot of that recently.

 

probably not accurate, probably just input voltage, zen 1 and 2 have on-die ldo regulators, same thing is probably true for zen 2

 

Thanks Captain Sarcasm. Even for more cores while pushing the limit that seems like insane voltage. We'll find out soon enough.